2013-05-07 00:17:29 +08:00
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; Test 8-bit compare and swap.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-MAIN
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT
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; Check compare and swap with a variable.
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; - CHECK is for the main loop.
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; - CHECK-SHIFT makes sure that the negated shift count used by the second
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; RLL is set up correctly. The negation is independent of the NILL and L
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; tested in CHECK. CHECK-SHIFT also checks that %r3 is not modified before
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; being used in the RISBG (in contrast to things like atomic addition,
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; which shift %r3 left so that %b is at the high end of the word).
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define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
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2013-07-14 14:24:09 +08:00
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; CHECK-MAIN-LABEL: f1:
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2016-04-30 03:53:16 +08:00
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; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
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; CHECK-MAIN: sll %r3, 3
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; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
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2013-05-07 00:17:29 +08:00
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; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
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2016-04-30 03:53:16 +08:00
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; CHECK-MAIN: rll %r2, [[OLD]], 8(%r3)
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2013-05-07 00:17:29 +08:00
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; CHECK-MAIN: risbg %r4, %r2, 32, 55, 0
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2013-05-28 18:41:11 +08:00
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; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
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2013-05-07 00:17:29 +08:00
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; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
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; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
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2016-04-30 03:53:16 +08:00
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; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
|
[SystemZ] Be more careful about inverting CC masks
System z branches have a mask to select which of the 4 CC values should
cause the branch to be taken. We can invert a branch by inverting the mask.
However, not all instructions can produce all 4 CC values, so inverting
the branch like this can lead to some oddities. For example, integer
comparisons only produce a CC of 0 (equal), 1 (less) or 2 (greater).
If an integer EQ is reversed to NE before instruction selection,
the branch will test for 1 or 2. If instead the branch is reversed
after instruction selection (by inverting the mask), it will test for
1, 2 or 3. Both are correct, but the second isn't really canonical.
This patch therefore keeps track of which CC values are possible
and uses this when inverting a mask.
Although this is mostly cosmestic, it fixes undefined behavior
for the CIJNLH in branch-08.ll. Another fix would have been
to mask out bit 0 when generating the fused compare and branch,
but the point of this patch is that we shouldn't need to do that
in the first place.
The patch also makes it easier to reuse CC results from other instructions.
llvm-svn: 187495
2013-07-31 20:30:20 +08:00
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; CHECK-MAIN: jl [[LOOP]]
|
2013-05-07 00:17:29 +08:00
|
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|
; CHECK-MAIN: [[EXIT]]:
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; CHECK-MAIN-NOT: %r2
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; CHECK-MAIN: br %r14
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;
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-SHIFT-LABEL: f1:
|
2016-04-30 03:53:16 +08:00
|
|
|
; CHECK-SHIFT: sll [[SHIFT:%r[1-9]+]], 3
|
2013-05-07 00:17:29 +08:00
|
|
|
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
|
|
|
|
; CHECK-SHIFT: rll
|
|
|
|
; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -8([[NEGSHIFT]])
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 22:24:07 +08:00
|
|
|
%pair = cmpxchg i8 *%src, i8 %cmp, i8 %swap seq_cst seq_cst
|
|
|
|
%res = extractvalue { i8, i1 } %pair, 0
|
2013-05-07 00:17:29 +08:00
|
|
|
ret i8 %res
|
|
|
|
}
|
|
|
|
|
|
|
|
; Check compare and swap with constants. We should force the constants into
|
|
|
|
; registers and use the sequence above.
|
|
|
|
define i8 @f2(i8 *%src) {
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f2:
|
2013-05-07 00:17:29 +08:00
|
|
|
; CHECK: lhi [[CMP:%r[0-9]+]], 42
|
|
|
|
; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
|
|
|
|
; CHECK: risbg
|
|
|
|
; CHECK: br %r14
|
|
|
|
;
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-SHIFT-LABEL: f2:
|
2013-05-07 00:17:29 +08:00
|
|
|
; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
|
|
|
|
; CHECK-SHIFT: risbg
|
|
|
|
; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
|
|
|
|
; CHECK-SHIFT: br %r14
|
IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 22:24:07 +08:00
|
|
|
%pair = cmpxchg i8 *%src, i8 42, i8 88 seq_cst seq_cst
|
|
|
|
%res = extractvalue { i8, i1 } %pair, 0
|
2013-05-07 00:17:29 +08:00
|
|
|
ret i8 %res
|
|
|
|
}
|
2017-09-29 00:22:54 +08:00
|
|
|
|
|
|
|
; Check generating the comparison result.
|
|
|
|
define i32 @f3(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
|
|
|
|
; CHECK-MAIN-LABEL: f3:
|
|
|
|
; CHECK-MAIN: risbg [[RISBG:%r[1-9]+]], %r3, 0, 189, 0{{$}}
|
|
|
|
; CHECK-MAIN: sll %r3, 3
|
|
|
|
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[RISBG]])
|
|
|
|
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
|
|
|
|
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
|
|
|
|
; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
|
2017-09-29 06:08:25 +08:00
|
|
|
; CHECK-MAIN: cr [[TMP]], %r4
|
|
|
|
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
|
2017-09-29 00:22:54 +08:00
|
|
|
; CHECK-MAIN: risbg %r5, [[TMP]], 32, 55, 0
|
|
|
|
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
|
|
|
|
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
|
|
|
|
; CHECK-MAIN: jl [[LOOP]]
|
|
|
|
; CHECK-MAIN: [[EXIT]]:
|
|
|
|
; CHECK-MAIN-NEXT: ipm %r2
|
|
|
|
; CHECK-MAIN-NEXT: afi %r2, -268435456
|
|
|
|
; CHECK-MAIN-NEXT: srl %r2, 31
|
|
|
|
; CHECK-MAIN-NOT: %r2
|
|
|
|
; CHECK-MAIN: br %r14
|
|
|
|
;
|
|
|
|
; CHECK-SHIFT-LABEL: f3:
|
|
|
|
; CHECK-SHIFT: sll [[SHIFT:%r[1-9]+]], 3
|
|
|
|
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
|
|
|
|
; CHECK-SHIFT: rll
|
|
|
|
; CHECK-SHIFT: rll {{%r[0-9]+}}, %r5, -8([[NEGSHIFT]])
|
|
|
|
%pair = cmpxchg i8 *%src, i8 %cmp, i8 %swap seq_cst seq_cst
|
|
|
|
%val = extractvalue { i8, i1 } %pair, 1
|
|
|
|
%res = zext i1 %val to i32
|
|
|
|
ret i32 %res
|
|
|
|
}
|
|
|
|
|