forked from OSchip/llvm-project
30 lines
826 B
Plaintext
30 lines
826 B
Plaintext
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#RUN: not llc -o - -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s
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# REQUIRES: global-isel, aarch64-registered-target
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--- |
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target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64-unknown-unknown"
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define i32 @g_concat_vectors() {
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ret i32 0
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}
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...
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---
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name: g_concat_vectors
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legalized: true
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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registers:
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- { id: 0, class: _, preferred-register: '' }
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- { id: 1, class: _, preferred-register: '' }
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liveins:
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body: |
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bb.0:
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; CHECK: Bad machine code: G_CONCAT_VECTOR num dest and source elements should match
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%0(<2 x s32>) = IMPLICIT_DEF
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%1(<2 x s32>) = IMPLICIT_DEF
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%2:_(<2 x s32>) = G_CONCAT_VECTORS %0, %1
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...
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