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llvm-project/llvm/test/MC/ARM/armv8.4a-trace.s

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[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418
2018-07-06 16:03:12 +08:00
// RUN: llvm-mc -triple arm -mattr=+v8.4a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-A32
// RUN: llvm-mc -triple thumb -mattr=+v8.4a -show-encoding < %s | FileCheck %s --check-prefix=CHECK-T32
// RUN: not llvm-mc -triple arm -mattr=-v8.4a -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-NO-V84
tsb csync
//CHECK-A32: tsb csync @ encoding: [0x12,0xf0,0x20,0xe3]
//CHECK-T32: tsb csync @ encoding: [0xaf,0xf3,0x12,0x80]
//CHECK-NO-V84: error: invalid instruction
//CHECK-NO-V84: tsb csync
//CHECK-NO-V84: ^