2017-08-02 08:28:10 +08:00
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; RUN: llc < %s -mcpu=generic -mtriple=i686-- -mattr=+cmov,cx16 -verify-machineinstrs | FileCheck %s
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2008-05-06 03:05:59 +08:00
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
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2010-10-05 19:16:24 +08:00
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define void @func(i32 %argc, i8** %argv) nounwind {
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2008-05-06 03:05:59 +08:00
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entry:
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%argc.addr = alloca i32 ; <i32*> [#uses=1]
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%argv.addr = alloca i8** ; <i8***> [#uses=1]
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%val1 = alloca i32 ; <i32*> [#uses=2]
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%val2 = alloca i32 ; <i32*> [#uses=15]
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%andt = alloca i32 ; <i32*> [#uses=2]
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%ort = alloca i32 ; <i32*> [#uses=2]
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%xort = alloca i32 ; <i32*> [#uses=2]
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%old = alloca i32 ; <i32*> [#uses=18]
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%temp = alloca i32 ; <i32*> [#uses=2]
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2012-04-14 06:47:00 +08:00
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%temp64 = alloca i64
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2008-05-06 03:05:59 +08:00
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store i32 %argc, i32* %argc.addr
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store i8** %argv, i8*** %argv.addr
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store i32 0, i32* %val1
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store i32 31, i32* %val2
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store i32 3855, i32* %andt
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store i32 3855, i32* %ort
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store i32 3855, i32* %xort
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store i32 4, i32* %temp
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2015-02-28 05:17:42 +08:00
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%tmp = load i32, i32* %temp
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: xaddl
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2011-09-27 08:17:29 +08:00
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%0 = atomicrmw add i32* %val1, i32 %tmp monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %0, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: xaddl
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2011-09-27 08:17:29 +08:00
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%1 = atomicrmw sub i32* %val2, i32 30 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %1, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: xaddl
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2011-09-27 08:17:29 +08:00
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%2 = atomicrmw add i32* %val2, i32 1 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %2, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: xaddl
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2011-09-27 08:17:29 +08:00
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%3 = atomicrmw sub i32* %val2, i32 1 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %3, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: andl
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%4 = atomicrmw and i32* %andt, i32 4080 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %4, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: orl
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%5 = atomicrmw or i32* %ort, i32 4080 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %5, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: xorl
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%6 = atomicrmw xor i32* %xort, i32 4080 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %6, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%7 = atomicrmw min i32* %val2, i32 16 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %7, i32* %old
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%neg = sub i32 0, 1 ; <i32> [#uses=1]
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%8 = atomicrmw min i32* %val2, i32 %neg monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %8, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%9 = atomicrmw max i32* %val2, i32 1 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %9, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%10 = atomicrmw max i32* %val2, i32 0 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %10, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%11 = atomicrmw umax i32* %val2, i32 65535 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %11, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%12 = atomicrmw umax i32* %val2, i32 10 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %12, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%13 = atomicrmw umin i32* %val2, i32 1 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %13, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: cmov
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; CHECK: lock
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; CHECK: cmpxchgl
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2011-09-27 08:17:29 +08:00
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%14 = atomicrmw umin i32* %val2, i32 10 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %14, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: xchgl %{{.*}}, {{.*}}(%esp)
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2011-09-27 08:17:29 +08:00
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%15 = atomicrmw xchg i32* %val2, i32 1976 monotonic
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2008-05-06 03:05:59 +08:00
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store i32 %15, i32* %old
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%neg1 = sub i32 0, 10 ; <i32> [#uses=1]
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: cmpxchgl
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IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 22:24:07 +08:00
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%pair16 = cmpxchg i32* %val2, i32 %neg1, i32 1 monotonic monotonic
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%16 = extractvalue { i32, i1 } %pair16, 0
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2008-05-06 03:05:59 +08:00
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store i32 %16, i32* %old
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2010-09-22 07:57:27 +08:00
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; CHECK: lock
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; CHECK: cmpxchgl
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IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 22:24:07 +08:00
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%pair17 = cmpxchg i32* %val2, i32 1976, i32 1 monotonic monotonic
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%17 = extractvalue { i32, i1 } %pair17, 0
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2008-05-06 03:05:59 +08:00
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store i32 %17, i32* %old
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2012-09-20 11:06:15 +08:00
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; CHECK: movl [[R17atomic:.*]], %eax
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2014-07-02 02:53:31 +08:00
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; CHECK: movl %eax, %[[R17mask:[a-z]*]]
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; CHECK: notl %[[R17mask]]
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; CHECK: orl $-1402, %[[R17mask]]
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2012-04-17 02:43:53 +08:00
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; CHECK: lock
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2012-09-20 11:06:15 +08:00
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; CHECK: cmpxchgl %[[R17mask]], [[R17atomic]]
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2012-04-17 02:43:53 +08:00
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; CHECK: jne
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; CHECK: movl %eax,
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2012-04-14 06:47:00 +08:00
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%18 = atomicrmw nand i32* %val2, i32 1401 monotonic
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store i32 %18, i32* %old
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; CHECK: notl
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; CHECK: notl
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2014-07-02 02:53:31 +08:00
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; CHECK: orl $252645135
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; CHECK: orl $252645135
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2012-04-14 06:47:00 +08:00
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; CHECK: lock
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; CHECK: cmpxchg8b
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%19 = atomicrmw nand i64* %temp64, i64 17361641481138401520 monotonic
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store i64 %19, i64* %temp64
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2008-05-06 03:05:59 +08:00
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ret void
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}
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2010-09-22 07:59:42 +08:00
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define void @test2(i32 addrspace(256)* nocapture %P) nounwind {
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entry:
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; CHECK: lock
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2010-11-30 06:34:55 +08:00
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; CHECK: cmpxchgl %{{.*}}, %gs:(%{{.*}})
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2010-09-22 07:59:42 +08:00
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IR: add "cmpxchg weak" variant to support permitted failure.
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
2014-06-13 22:24:07 +08:00
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%pair0 = cmpxchg i32 addrspace(256)* %P, i32 0, i32 1 monotonic monotonic
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%0 = extractvalue { i32, i1 } %pair0, 0
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2010-09-22 07:59:42 +08:00
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ret void
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}
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