forked from OSchip/llvm-project
83 lines
3.5 KiB
LLVM
83 lines
3.5 KiB
LLVM
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tahiti -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
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declare i32 @llvm.amdgcn.writelane(i32, i32, i32) #0
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; CHECK-LABEL: {{^}}test_writelane_sreg:
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; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @test_writelane_sreg(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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%oldval = load i32, i32 addrspace(1)* %out
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_writelane_imm_sreg:
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; CHECK: v_writelane_b32 v{{[0-9]+}}, 32, s{{[0-9]+}}
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define amdgpu_kernel void @test_writelane_imm_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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%oldval = load i32, i32 addrspace(1)* %out
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%writelane = call i32 @llvm.amdgcn.writelane(i32 32, i32 %src1, i32 %oldval)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_writelane_vreg_lane:
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; CHECK: v_readfirstlane_b32 [[LANE:s[0-9]+]], v{{[0-9]+}}
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; CHECK: v_writelane_b32 v{{[0-9]+}}, 12, [[LANE]]
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define amdgpu_kernel void @test_writelane_vreg_lane(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) #1 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.in = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 %tid
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%args = load <2 x i32>, <2 x i32> addrspace(1)* %gep.in
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%oldval = load i32, i32 addrspace(1)* %out
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%lane = extractelement <2 x i32> %args, i32 1
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%writelane = call i32 @llvm.amdgcn.writelane(i32 12, i32 %lane, i32 %oldval)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; TODO: m0 should be folded.
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; CHECK-LABEL: {{^}}test_writelane_m0_sreg:
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; CHECK: s_mov_b32 m0, -1
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; CHECK: s_mov_b32 [[COPY_M0:s[0-9]+]], m0
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; CHECK: v_writelane_b32 v{{[0-9]+}}, [[COPY_M0]], s{{[0-9]+}}
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define amdgpu_kernel void @test_writelane_m0_sreg(i32 addrspace(1)* %out, i32 %src1) #1 {
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%oldval = load i32, i32 addrspace(1)* %out
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%m0 = call i32 asm "s_mov_b32 m0, -1", "={M0}"()
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %src1, i32 %oldval)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_writelane_imm:
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; CHECK: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 32
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define amdgpu_kernel void @test_writelane_imm(i32 addrspace(1)* %out, i32 %src0) #1 {
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%oldval = load i32, i32 addrspace(1)* %out
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 32, i32 %oldval) #0
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_writelane_sreg_oldval:
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; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], s{{[0-9]+}}
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; CHECK: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @test_writelane_sreg_oldval(i32 inreg %oldval, i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 %oldval)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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; CHECK-LABEL: {{^}}test_writelane_imm_oldval:
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; CHECK: v_mov_b32_e32 [[OLDVAL:v[0-9]+]], 42
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; CHECK: v_writelane_b32 [[OLDVAL]], s{{[0-9]+}}, s{{[0-9]+}}
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define amdgpu_kernel void @test_writelane_imm_oldval(i32 addrspace(1)* %out, i32 %src0, i32 %src1) #1 {
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%writelane = call i32 @llvm.amdgcn.writelane(i32 %src0, i32 %src1, i32 42)
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store i32 %writelane, i32 addrspace(1)* %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #2
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attributes #0 = { nounwind readnone convergent }
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attributes #1 = { nounwind }
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attributes #2 = { nounwind readnone }
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