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llvm-project/llvm/test/CodeGen/X86/stack-folding-bmi2.mir

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[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=x86_64-- -run-pass=greedy %s | FileCheck %s
# Tests for stack folding MULX. Doing this as a MIR test to ensure MULX is used and not legacy MUL.
--- |
; Function Attrs: nounwind
define i32 @stack_fold_mulx_u32(i32 %a0, i32 %a1) #0 {
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
tail call void asm sideeffect "nop", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%1 = zext i32 %a0 to i128
%2 = zext i32 %a1 to i128
%3 = mul i128 %1, %2
%4 = lshr i128 %3, 32
%5 = trunc i128 %4 to i32
ret i32 %5
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
}
; Function Attrs: nounwind
define i64 @stack_fold_mulx_u64(i64 %a0, i64 %a1) #0 {
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
tail call void asm sideeffect "nop", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
%1 = zext i64 %a0 to i128
%2 = zext i64 %a1 to i128
%3 = mul i128 %1, %2
%4 = lshr i128 %3, 64
%5 = trunc i128 %4 to i64
ret i64 %5
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
}
; Function Attrs: nounwind
declare void @llvm.stackprotector(i8*, i8**) #1
attributes #0 = { nounwind "target-features"="+bmi2" }
attributes #1 = { nounwind }
...
---
name: stack_fold_mulx_u32
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr32 }
- { id: 2, class: fr64 }
- { id: 3, class: gr32 }
- { id: 4, class: gr32 }
liveins:
- { reg: '$edi', virtual-reg: '%0' }
- { reg: '$esi', virtual-reg: '%1' }
body: |
bb.0 (%ir-block.0):
liveins: $edi, $esi
; CHECK-LABEL: name: stack_fold_mulx_u32
; CHECK: liveins: $edi, $esi
; CHECK: MOV32mr %stack.0, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.1)
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
; CHECK: $edx = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load 4 from %stack.1)
; CHECK: %3:gr32, dead %4:gr32 = MULX32rm %stack.0, 1, $noreg, 0, $noreg, implicit $edx :: (load 4 from %stack.0)
; CHECK: $eax = COPY %3
; CHECK: RET 0, $eax
%1:gr32 = COPY $esi
%0:gr32 = COPY $edi
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
$edx = COPY %0
%3:gr32, dead %4:gr32 = MULX32rr %1, implicit killed $edx
$eax = COPY %3
RET 0, killed $eax
...
---
name: stack_fold_mulx_u64
[Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing Summary: This catches malformed mir files which specify alignment as log2 instead of pow2. See https://reviews.llvm.org/D65945 for reference, This is patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Reviewers: courbet Subscribers: MatzeB, qcolombet, dschuff, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, jsji, Petar.Avramovic, asbirlea, s.egerton, pzheng, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67433 llvm-svn: 371608
2019-09-11 19:16:48 +08:00
alignment: 16
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
tracksRegLiveness: true
registers:
- { id: 0, class: gr64 }
- { id: 1, class: gr64 }
- { id: 2, class: fr64 }
- { id: 3, class: gr64 }
- { id: 4, class: gr64 }
liveins:
- { reg: '$rdi', virtual-reg: '%0' }
- { reg: '$rsi', virtual-reg: '%1' }
body: |
bb.0 (%ir-block.0):
liveins: $rdi, $rsi
; CHECK-LABEL: name: stack_fold_mulx_u64
; CHECK: liveins: $rdi, $rsi
; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.0)
; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdi :: (store 8 into %stack.1)
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
; CHECK: $rdx = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load 8 from %stack.1)
; CHECK: %3:gr64, dead %4:gr64 = MULX64rm %stack.0, 1, $noreg, 0, $noreg, implicit $rdx :: (load 8 from %stack.0)
; CHECK: $rax = COPY %3
; CHECK: RET 0, $rax
%1:gr64 = COPY $rsi
%0:gr64 = COPY $rdi
[X86] Clean up some mir tests with INLINEASM to avoid regdef or to correct the immediate for the regdef. The immediate used for the regdef is the encoding for the register class in the enum generated by tablegen. This encoding will change any time a new register class is added. Since the number is part of the input, this means it can become stale. This change modifies some test to avoid this kind of immediate all together. And updates one test to use the current encoding of GR64.
2020-04-18 11:45:58 +08:00
INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
[X86] Move stack folding test for MULX to a MIR test. Add a MULX32 case as well A future patch may stop using MULX by default so use MIR to ensure we're always testing MULX. Add the 32-bit case that we couldn't do in the 64-bit mode IR test due to it being promoted to a 64-bit mul. llvm-svn: 348972
2018-12-13 04:50:24 +08:00
$rdx = COPY %0
%3:gr64, dead %4:gr64 = MULX64rr %1, implicit killed $rdx
$rax = COPY %3
RET 0, killed $rax
...