forked from OSchip/llvm-project
60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s -check-prefix=DEFAULT
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; RUN: llc < %s -mtriple=i686-pc-linux-gnu -x86-experimental-pref-innermost-loop-alignment=5 | FileCheck %s -check-prefix=ALIGN32
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; RUN: llc < %s -mtriple=i686-pc-linux-gnu -x86-experimental-pref-loop-alignment=5 -x86-experimental-pref-innermost-loop-alignment=6 | FileCheck %s -check-prefix=ALIGN64
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declare void @foo()
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define void @test(i32 %n, i32 %m) {
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; DEFAULT-LABEL: test:
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; DEFAULT: .p2align 4, 0x90
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; DEFAULT-NEXT: .LBB0_1: # %outer
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; DEFAULT-NEXT: # =>This Loop Header: Depth=1
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; DEFAULT-NEXT: # Child Loop BB0_2 Depth 2
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; DEFAULT: .p2align 4, 0x90
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; DEFAULT-NEXT: .LBB0_2: # %inner
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; DEFAULT-NEXT: # Parent Loop BB0_1 Depth=1
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; ALIGN32-LABEL: test:
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; ALIGN32: .p2align 4, 0x90
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; ALIGN32-NEXT: .LBB0_1: # %outer
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; ALIGN32-NEXT: # =>This Loop Header: Depth=1
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; ALIGN32-NEXT: # Child Loop BB0_2 Depth 2
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; ALIGN32: .p2align 5, 0x90
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; ALIGN32-NEXT: .LBB0_2: # %inner
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; ALIGN32-NEXT: # Parent Loop BB0_1 Depth=1
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; ALIGN32-NEXT: # => This Inner Loop Header: Depth=2
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; ALIGN64-LABEL: test:
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; ALIGN64: .p2align 5, 0x90
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; ALIGN64-NEXT: .LBB0_1: # %outer
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; ALIGN64-NEXT: # =>This Loop Header: Depth=1
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; ALIGN64-NEXT: # Child Loop BB0_2 Depth 2
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; ALIGN64: .p2align 6, 0x90
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; ALIGN64-NEXT: .LBB0_2: # %inner
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; ALIGN64-NEXT: # Parent Loop BB0_1 Depth=1
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; ALIGN64-NEXT: # => This Inner Loop Header: Depth=2
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entry:
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br label %outer
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outer:
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%outer.iv = phi i32 [0, %entry], [%outer.iv.next, %outer_bb]
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br label %inner
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inner:
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%inner.iv = phi i32 [0, %outer], [%inner.iv.next, %inner]
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call void @foo()
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%inner.iv.next = add i32 %inner.iv, 1
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%inner.cond = icmp ne i32 %inner.iv.next, %m
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br i1 %inner.cond, label %inner, label %outer_bb
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outer_bb:
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%outer.iv.next = add i32 %outer.iv, 1
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%outer.cond = icmp ne i32 %outer.iv.next, %n
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br i1 %outer.cond, label %outer, label %exit
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exit:
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ret void
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}
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