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[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512vbmi,+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vbmi,+avx512vl --show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
declare <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <16 x i8>@test_int_x86_avx512_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_permvar_qi_128:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermb %xmm0, %xmm1, %xmm0 # encoding: [0x62,0xf2,0x75,0x08,0x8d,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
ret <16 x i8> %res
}
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
define <16 x i8>@test_int_x86_avx512_mask_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_permvar_qi_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermb %xmm0, %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf2,0x75,0x09,0x8d,0xd0]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_permvar_qi_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermb %xmm0, %xmm1, %xmm2 {%k1} # encoding: [0x62,0xf2,0x75,0x09,0x8d,0xd0]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
%res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <16 x i8> %res
}
define <16 x i8>@test_int_x86_avx512_maskz_permvar_qi_128(<16 x i8> %x0, <16 x i8> %x1, i16 %x3) {
; X86-LABEL: test_int_x86_avx512_maskz_permvar_qi_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermb %xmm0, %xmm1, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0x89,0x8d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_permvar_qi_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermb %xmm0, %xmm1, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0x89,0x8d,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.permvar.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
ret <16 x i8> %res
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
}
declare <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <32 x i8>@test_int_x86_avx512_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_permvar_qi_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermb %ymm0, %ymm1, %ymm0 # encoding: [0x62,0xf2,0x75,0x28,0x8d,0xc0]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
ret <32 x i8> %res
}
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
define <32 x i8>@test_int_x86_avx512_mask_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_permvar_qi_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermb %ymm0, %ymm1, %ymm2 {%k1} # encoding: [0x62,0xf2,0x75,0x29,0x8d,0xd0]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_permvar_qi_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermb %ymm0, %ymm1, %ymm2 {%k1} # encoding: [0x62,0xf2,0x75,0x29,0x8d,0xd0]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
%res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <32 x i8> %res
}
define <32 x i8>@test_int_x86_avx512_maskz_permvar_qi_256(<32 x i8> %x0, <32 x i8> %x1, i32 %x3) {
; X86-LABEL: test_int_x86_avx512_maskz_permvar_qi_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermb %ymm0, %ymm1, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0xa9,0x8d,0xc0]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_permvar_qi_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermb %ymm0, %ymm1, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0xa9,0x8d,0xc0]
; X64-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.permvar.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
ret <32 x i8> %res
[X86] Remove mask arguments from permvar builtins/intrinsics. Use a select in IR instead. Someday maybe we'll use selects for all intrinsics. llvm-svn: 332824
2018-05-21 07:34:04 +08:00
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
declare <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <16 x i8>@test_int_x86_avx512_pmultishift_qb_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_pmultishift_qb_128:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmultishiftqb %xmm1, %xmm0, %xmm0 # encoding: [0x62,0xf2,0xfd,0x08,0x83,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
ret <16 x i8> %res
}
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
define <16 x i8>@test_int_x86_avx512_mask_pmultishift_qb_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_pmultishift_qb_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpmultishiftqb %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf2,0xfd,0x09,0x83,0xd1]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_pmultishift_qb_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpmultishiftqb %xmm1, %xmm0, %xmm2 {%k1} # encoding: [0x62,0xf2,0xfd,0x09,0x83,0xd1]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %xmm2, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc2]
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <16 x i8> %res
}
define <16 x i8>@test_int_x86_avx512_maskz_pmultishift_qb_128(<16 x i8> %x0, <16 x i8> %x1, i16 %x3) {
; X86-LABEL: test_int_x86_avx512_maskz_pmultishift_qb_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpmultishiftqb %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0x83,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_pmultishift_qb_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpmultishiftqb %xmm1, %xmm0, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0x89,0x83,0xc1]
; X64-NEXT: retq # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.pmultishift.qb.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> zeroinitializer, i16 %x3)
ret <16 x i8> %res
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
}
declare <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <32 x i8>@test_int_x86_avx512_pmultishift_qb_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_pmultishift_qb_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmultishiftqb %ymm1, %ymm0, %ymm0 # encoding: [0x62,0xf2,0xfd,0x28,0x83,0xc1]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
ret <32 x i8> %res
}
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
define <32 x i8>@test_int_x86_avx512_mask_pmultishift_qb_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
; X86-LABEL: test_int_x86_avx512_mask_pmultishift_qb_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpmultishiftqb %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf2,0xfd,0x29,0x83,0xd1]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_pmultishift_qb_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpmultishiftqb %ymm1, %ymm0, %ymm2 {%k1} # encoding: [0x62,0xf2,0xfd,0x29,0x83,0xd1]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %ymm2, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc2]
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
; X64-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <32 x i8> %res
}
define <32 x i8>@test_int_x86_avx512_maskz_pmultishift_qb_256(<32 x i8> %x0, <32 x i8> %x1, i32 %x3) {
; X86-LABEL: test_int_x86_avx512_maskz_pmultishift_qb_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpmultishiftqb %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0xa9,0x83,0xc1]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_pmultishift_qb_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpmultishiftqb %ymm1, %ymm0, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0xfd,0xa9,0x83,0xc1]
; X64-NEXT: retq # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.pmultishift.qb.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> zeroinitializer, i32 %x3)
ret <32 x i8> %res
[X86] Remove mask parameter from avx512 pmultishiftqb intrinsics. Use select in IR instead. Fixes PR40259 llvm-svn: 351035
2019-01-14 16:46:45 +08:00
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
declare <16 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <16 x i8>@test_int_x86_avx512_vpermi2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_vpermi2var_qi_128:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermt2b %xmm2, %xmm1, %xmm0 # encoding: [0x62,0xf2,0x75,0x08,0x7d,0xc2]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
ret <16 x i8> %res
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
define <16 x i8>@test_int_x86_avx512_mask_vpermi2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_vpermi2var_qi_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermi2b %xmm2, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x09,0x75,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_vpermi2var_qi_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermi2b %xmm2, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x09,0x75,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <16 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <16 x i8> %res
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
}
declare <32 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <32 x i8>@test_int_x86_avx512_vpermi2var_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_vpermi2var_qi_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermt2b %ymm2, %ymm1, %ymm0 # encoding: [0x62,0xf2,0x75,0x28,0x7d,0xc2]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
ret <32 x i8> %res
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
define <32 x i8>@test_int_x86_avx512_mask_vpermi2var_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_vpermi2var_qi_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermi2b %ymm2, %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x29,0x75,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_vpermi2var_qi_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermi2b %ymm2, %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x29,0x75,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <32 x i8> @llvm.x86.avx512.mask.vpermi2var.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <32 x i8> %res
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
}
declare <16 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <16 x i8>@test_int_x86_avx512_vpermt2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_vpermt2var_qi_128:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermi2b %xmm2, %xmm1, %xmm0 # encoding: [0x62,0xf2,0x75,0x08,0x75,0xc2]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <16 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 -1)
ret <16 x i8> %res
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
define <16 x i8>@test_int_x86_avx512_mask_vpermt2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_vpermt2var_qi_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermt2b %xmm2, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x09,0x7d,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_vpermt2var_qi_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermt2b %xmm2, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x09,0x7d,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %xmm1, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <16 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <16 x i8> %res
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
}
declare <32 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
define <32 x i8>@test_int_x86_avx512_vpermt2var_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2) {
; CHECK-LABEL: test_int_x86_avx512_vpermt2var_qi_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpermi2b %ymm2, %ymm1, %ymm0 # encoding: [0x62,0xf2,0x75,0x28,0x75,0xc2]
; CHECK-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%res = call <32 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 -1)
ret <32 x i8> %res
}
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
define <32 x i8>@test_int_x86_avx512_mask_vpermt2var_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_mask_vpermt2var_qi_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermt2b %ymm2, %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x29,0x7d,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X86-NEXT: vmovdqa %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_mask_vpermt2var_qi_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermt2b %ymm2, %ymm0, %ymm1 {%k1} # encoding: [0x62,0xf2,0x7d,0x29,0x7d,0xca]
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
; X64-NEXT: vmovdqa %ymm1, %ymm0 # EVEX TO VEX Compression encoding: [0xc5,0xfd,0x6f,0xc1]
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <32 x i8> @llvm.x86.avx512.mask.vpermt2var.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
[X86] Split masked instruction tests to enable D60940. We need to split tests that rely on isel duplicating operations for different masking conditions. Repeating the operation is more costly than emitting the masking separately. The change here is a mechanical splitting of tests that call multiple intrinsics in one function into separate functions that call one intrinsic. We could obviously avoid the splitting by giving the intrinsics different operands, but that would need closer scrutiny than just splitting.
2020-03-25 10:03:36 +08:00
ret <32 x i8> %res
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
}
declare <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8>, <16 x i8>, <16 x i8>, i16)
define <16 x i8>@test_int_x86_avx512_maskz_vpermt2var_qi_128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_maskz_vpermt2var_qi_128:
; X86: # %bb.0:
; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 # encoding: [0xc5,0xf8,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermi2b %xmm2, %xmm1, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0x89,0x75,0xc2]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_vpermt2var_qi_128:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermi2b %xmm2, %xmm1, %xmm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0x89,0x75,0xc2]
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <16 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.128(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, i16 %x3)
ret <16 x i8> %res
}
declare <32 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.256(<32 x i8>, <32 x i8>, <32 x i8>, i32)
define <32 x i8>@test_int_x86_avx512_maskz_vpermt2var_qi_256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3) {
[X86][AVX512] Cleanup intrinsics tests Ensure we test on 32-bit and 64-bit targets, and strip -mcpu usage. Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible. llvm-svn: 333843
2018-06-03 22:56:04 +08:00
; X86-LABEL: test_int_x86_avx512_maskz_vpermt2var_qi_256:
; X86: # %bb.0:
; X86-NEXT: kmovd {{[0-9]+}}(%esp), %k1 # encoding: [0xc4,0xe1,0xf9,0x90,0x4c,0x24,0x04]
; X86-NEXT: vpermi2b %ymm2, %ymm1, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0xa9,0x75,0xc2]
; X86-NEXT: retl # encoding: [0xc3]
;
; X64-LABEL: test_int_x86_avx512_maskz_vpermt2var_qi_256:
; X64: # %bb.0:
; X64-NEXT: kmovd %edi, %k1 # encoding: [0xc5,0xfb,0x92,0xcf]
; X64-NEXT: vpermi2b %ymm2, %ymm1, %ymm0 {%k1} {z} # encoding: [0x62,0xf2,0x75,0xa9,0x75,0xc2]
; X64-NEXT: retq # encoding: [0xc3]
[X86] Remove masked vpermi2var/vpermt2var intrinsics and autoupgrade. We have unmasked intrinsics now and wrap them with a select. This is a net reduction of 36 intrinsics from before the unmasked intrinsics were added. llvm-svn: 333388
2018-05-29 13:22:05 +08:00
%res = call <32 x i8> @llvm.x86.avx512.maskz.vpermt2var.qi.256(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, i32 %x3)
ret <32 x i8> %res
}