forked from OSchip/llvm-project
548 lines
23 KiB
Plaintext
548 lines
23 KiB
Plaintext
|
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||
|
|
# RUN: llc -run-pass arm-mve-vpt-opts %s -o - | FileCheck %s
|
||
|
|
|
||
|
|
--- |
|
||
|
|
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||
|
|
target triple = "thumbv8.1m.main-arm-none-eabi"
|
||
|
|
|
||
|
|
; Functions are intentionally left blank - see the MIR sequences below.
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond_and_swapped_operands(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @triple_vcmp(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @killed_vccr_values(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @predicated_vcmps(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @flt_with_swapped_operands(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @different_opcodes(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @incorrect_condcode(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
define arm_aapcs_vfpcc <4 x float> @vpr_or_vccr_write_between_vcmps(<4 x float> %inactive1) #0 {
|
||
|
|
entry:
|
||
|
|
ret <4 x float> %inactive1
|
||
|
|
}
|
||
|
|
|
||
|
|
attributes #0 = { "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" }
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: vcmp_with_opposite_cond
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: vcmp_with_opposite_cond
|
||
|
|
; CHECK: bb.0:
|
||
|
|
; CHECK: successors: %bb.1(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg
|
||
|
|
; CHECK: bb.1:
|
||
|
|
; CHECK: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg
|
||
|
|
; CHECK: bb.2:
|
||
|
|
; CHECK: successors: %bb.3(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg
|
||
|
|
; CHECK: bb.3:
|
||
|
|
; CHECK: successors: %bb.4(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg
|
||
|
|
; CHECK: bb.4:
|
||
|
|
; CHECK: successors: %bb.5(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg
|
||
|
|
; CHECK: bb.5:
|
||
|
|
; CHECK: successors: %bb.6(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg
|
||
|
|
; CHECK: bb.6:
|
||
|
|
; CHECK: successors: %bb.7(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||
|
|
; CHECK: bb.7:
|
||
|
|
; CHECK: successors: %bb.8(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg
|
||
|
|
; CHECK: bb.8:
|
||
|
|
; CHECK: successors: %bb.9(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg
|
||
|
|
; CHECK: bb.9:
|
||
|
|
; CHECK: successors: %bb.10(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg
|
||
|
|
; CHECK: bb.10:
|
||
|
|
; CHECK: successors: %bb.11(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg
|
||
|
|
; CHECK: bb.11:
|
||
|
|
; CHECK: successors: %bb.12(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg
|
||
|
|
; CHECK: bb.12:
|
||
|
|
; CHECK: successors: %bb.13(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg
|
||
|
|
; CHECK: bb.13:
|
||
|
|
; CHECK: successors: %bb.14(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg
|
||
|
|
; CHECK: bb.14:
|
||
|
|
; CHECK: successors: %bb.15(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg
|
||
|
|
; CHECK: bb.15:
|
||
|
|
; CHECK: successors: %bb.16(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg
|
||
|
|
; CHECK: bb.16:
|
||
|
|
; CHECK: successors: %bb.17(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg
|
||
|
|
; CHECK: bb.17:
|
||
|
|
; CHECK: successors: %bb.18(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg
|
||
|
|
; CHECK: bb.18:
|
||
|
|
; CHECK: successors: %bb.19(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg
|
||
|
|
; CHECK: bb.19:
|
||
|
|
; CHECK: successors: %bb.20(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg
|
||
|
|
; CHECK: bb.20:
|
||
|
|
; CHECK: successors: %bb.21(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg
|
||
|
|
; CHECK: bb.21:
|
||
|
|
; CHECK: successors: %bb.22(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg
|
||
|
|
; CHECK: bb.22:
|
||
|
|
; CHECK: [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
;
|
||
|
|
; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
%3:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.1:
|
||
|
|
%5:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%6:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.2:
|
||
|
|
%7:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%8:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.3:
|
||
|
|
%9:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%10:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.4:
|
||
|
|
%11:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%12:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.5:
|
||
|
|
%13:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%14:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.6:
|
||
|
|
%15:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.7:
|
||
|
|
%17:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%18:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.8:
|
||
|
|
%19:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%20:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.9:
|
||
|
|
%21:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%22:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.10:
|
||
|
|
%23:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%24:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.11:
|
||
|
|
%25:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%26:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.12:
|
||
|
|
%27:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%28:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.13:
|
||
|
|
%29:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%30:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.14:
|
||
|
|
%31:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%32:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.15:
|
||
|
|
%33:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%34:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.16:
|
||
|
|
%35:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%36:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.17:
|
||
|
|
%37:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%38:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.18:
|
||
|
|
%39:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%40:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.19:
|
||
|
|
%41:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%42:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.20:
|
||
|
|
%43:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%44:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.21:
|
||
|
|
%45:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||
|
|
%46:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.22:
|
||
|
|
; There shouldn't be any exception for $zr, so the second VCMP should
|
||
|
|
; be transformed into a VPNOT.
|
||
|
|
%47:vccr = MVE_VCMPu8r %0:mqpr, $zr, 10, 0, $noreg
|
||
|
|
%48:vccr = MVE_VCMPu8r %0:mqpr, $zr, 11, 0, $noreg
|
||
|
|
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: vcmp_with_opposite_cond_and_swapped_operands
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands
|
||
|
|
; CHECK: bb.0:
|
||
|
|
; CHECK: successors: %bb.1(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg
|
||
|
|
; CHECK: bb.1:
|
||
|
|
; CHECK: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg
|
||
|
|
; CHECK: bb.2:
|
||
|
|
; CHECK: successors: %bb.3(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg
|
||
|
|
; CHECK: bb.3:
|
||
|
|
; CHECK: successors: %bb.4(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg
|
||
|
|
; CHECK: bb.4:
|
||
|
|
; CHECK: successors: %bb.5(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||
|
|
; CHECK: bb.5:
|
||
|
|
; CHECK: successors: %bb.6(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg
|
||
|
|
; CHECK: bb.6:
|
||
|
|
; CHECK: successors: %bb.7(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg
|
||
|
|
; CHECK: bb.7:
|
||
|
|
; CHECK: successors: %bb.8(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg
|
||
|
|
; CHECK: bb.8:
|
||
|
|
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
;
|
||
|
|
; Tests that VCMPs with an opposite condition and swapped operands are
|
||
|
|
; correctly converted into VPNOTs.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.1:
|
||
|
|
%4:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%5:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.2:
|
||
|
|
%6:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%7:vccr = MVE_VCMPi8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.3:
|
||
|
|
%8:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%9:vccr = MVE_VCMPs16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.4:
|
||
|
|
%10:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%11:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.5:
|
||
|
|
%12:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%13:vccr = MVE_VCMPs8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.6:
|
||
|
|
%14:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%15:vccr = MVE_VCMPu16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.7:
|
||
|
|
%16:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%17:vccr = MVE_VCMPu32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.8:
|
||
|
|
%18:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%19:vccr = MVE_VCMPu8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: triple_vcmp
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
;
|
||
|
|
; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first
|
||
|
|
; becomes a VPNOT.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
; CHECK-LABEL: name: triple_vcmp
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: killed_vccr_values
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
bb.0:
|
||
|
|
;
|
||
|
|
; Tests that, if the result of the VCMP is killed before the
|
||
|
|
; second VCMP (that will be converted into a VPNOT) is found,
|
||
|
|
; the kill flag is removed.
|
||
|
|
;
|
||
|
|
; CHECK-LABEL: name: killed_vccr_values
|
||
|
|
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPf16_]], undef [[MVE_VORR]]
|
||
|
|
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, killed %2:vccr, undef %3:mqpr
|
||
|
|
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: predicated_vcmps
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: predicated_vcmps
|
||
|
|
; CHECK: bb.0:
|
||
|
|
; CHECK: successors: %bb.1(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi16_]]
|
||
|
|
; CHECK: [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_]]
|
||
|
|
; CHECK: bb.1:
|
||
|
|
; CHECK: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi32_]]
|
||
|
|
; CHECK: [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_]]
|
||
|
|
; CHECK: bb.2:
|
||
|
|
; CHECK: successors: %bb.3(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf16_]]
|
||
|
|
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf16_]]
|
||
|
|
; CHECK: bb.3:
|
||
|
|
; CHECK: successors: %bb.4(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf32_]]
|
||
|
|
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf32_]]
|
||
|
|
; CHECK: bb.4:
|
||
|
|
; CHECK: successors: %bb.5(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi16_3]]
|
||
|
|
; CHECK: [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_3]]
|
||
|
|
; CHECK: bb.5:
|
||
|
|
; CHECK: [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi32_3]]
|
||
|
|
; CHECK: [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_3]]
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
;
|
||
|
|
; Tests that predicated VCMPs are not replaced.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 1, %2:vccr
|
||
|
|
%4:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %2:vccr
|
||
|
|
|
||
|
|
bb.1:
|
||
|
|
%5:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%6:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 1, %5:vccr
|
||
|
|
%7:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %5:vccr
|
||
|
|
|
||
|
|
bb.2:
|
||
|
|
%8:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%9:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 1, %8:vccr
|
||
|
|
%10:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 1, %8:vccr
|
||
|
|
|
||
|
|
bb.3:
|
||
|
|
%11:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%12:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 1, %11:vccr
|
||
|
|
%13:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 1, %11:vccr
|
||
|
|
|
||
|
|
bb.4:
|
||
|
|
%14:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%15:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 1, %14:vccr
|
||
|
|
%16:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %14:vccr
|
||
|
|
|
||
|
|
bb.5:
|
||
|
|
%17:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%18:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 1, %17:vccr
|
||
|
|
%19:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %17:vccr
|
||
|
|
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: flt_with_swapped_operands
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: flt_with_swapped_operands
|
||
|
|
; CHECK: bb.0:
|
||
|
|
; CHECK: successors: %bb.1(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||
|
|
; CHECK: bb.1:
|
||
|
|
; CHECK: successors: %bb.2(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||
|
|
; CHECK: bb.2:
|
||
|
|
; CHECK: successors: %bb.3(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
; CHECK: bb.3:
|
||
|
|
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
;
|
||
|
|
; Tests that float VCMPs with an opposite condition and swapped operands
|
||
|
|
; are not transformed into VPNOTs.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.1:
|
||
|
|
%4:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%5:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||
|
|
|
||
|
|
bb.2:
|
||
|
|
%6:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%7:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||
|
|
|
||
|
|
bb.3:
|
||
|
|
%8:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%9:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: different_opcodes
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
;
|
||
|
|
; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP
|
||
|
|
; is not transformed into a VPNOT.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
; CHECK-LABEL: name: different_opcodes
|
||
|
|
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 0, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 1, 1, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: incorrect_condcode
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
; CHECK-LABEL: name: incorrect_condcode
|
||
|
|
; CHECK: bb.0:
|
||
|
|
; CHECK: successors: %bb.1(0x80000000)
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||
|
|
; CHECK: bb.1:
|
||
|
|
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
;
|
||
|
|
; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not
|
||
|
|
; the opposite CondCode.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||
|
|
bb.1:
|
||
|
|
%4:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
%5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|
||
|
|
---
|
||
|
|
name: vpr_or_vccr_write_between_vcmps
|
||
|
|
alignment: 4
|
||
|
|
body: |
|
||
|
|
;
|
||
|
|
; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if
|
||
|
|
; VCCR/VPR is written to in-between.
|
||
|
|
;
|
||
|
|
bb.0:
|
||
|
|
; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps
|
||
|
|
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg
|
||
|
|
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg
|
||
|
|
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg
|
||
|
|
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||
|
|
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg
|
||
|
|
%3:vccr = MVE_VPNOT killed %2:vccr, 0, $noreg
|
||
|
|
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg
|
||
|
|
tBX_RET 14, $noreg, implicit %0:mqpr
|
||
|
|
...
|