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llvm-project/llvm/test/CodeGen/X86/known-bits.ll

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[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=X64
define void @knownbits_zext_in_reg(i8*) nounwind {
; X32-LABEL: knownbits_zext_in_reg:
; X32: # BB#0: # %BB
; X32-NEXT: pushl %ebp
; X32-NEXT: pushl %ebx
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movzbl (%eax), %eax
; X32-NEXT: imull $101, %eax, %eax
; X32-NEXT: andl $16384, %eax # imm = 0x4000
; X32-NEXT: shrl $14, %eax
; X32-NEXT: movzbl %al, %eax
; X32-NEXT: vmovd %eax, %xmm0
[X86][SSE] Add support for combining AND bitmasks to shuffles. llvm-svn: 288365
2016-12-01 23:41:40 +08:00
; X32-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: vpextrd $1, %xmm0, %ebp
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: xorl %ecx, %ecx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: vmovd %xmm0, %esi
; X32-NEXT: vpextrd $2, %xmm0, %edi
; X32-NEXT: vpextrd $3, %xmm0, %ebx
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_1: # %CF
; X32-NEXT: # =>This Loop Header: Depth=1
; X32-NEXT: # Child Loop BB0_2 Depth 2
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: movl %ebp, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: divl %ebp
; X32-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: movl %esi, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: divl %esi
; X32-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: movl %edi, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: divl %edi
; X32-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: movl %ebx, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X32-NEXT: divl %ebx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X32-NEXT: .p2align 4, 0x90
; X32-NEXT: .LBB0_2: # %CF237
; X32-NEXT: # Parent Loop BB0_1 Depth=1
; X32-NEXT: # => This Inner Loop Header: Depth=2
; X32-NEXT: testb %cl, %cl
; X32-NEXT: jne .LBB0_2
; X32-NEXT: jmp .LBB0_1
;
; X64-LABEL: knownbits_zext_in_reg:
; X64: # BB#0: # %BB
; X64-NEXT: movzbl (%rdi), %eax
; X64-NEXT: imull $101, %eax, %eax
; X64-NEXT: andl $16384, %eax # imm = 0x4000
; X64-NEXT: shrl $14, %eax
; X64-NEXT: movzbl %al, %eax
; X64-NEXT: vmovd %eax, %xmm0
[X86][SSE] Add support for combining AND bitmasks to shuffles. llvm-svn: 288365
2016-12-01 23:41:40 +08:00
; X64-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: vpextrd $1, %xmm0, %r8d
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: xorl %esi, %esi
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: vmovd %xmm0, %r9d
; X64-NEXT: vpextrd $2, %xmm0, %edi
; X64-NEXT: vpextrd $3, %xmm0, %ecx
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_1: # %CF
; X64-NEXT: # =>This Loop Header: Depth=1
; X64-NEXT: # Child Loop BB0_2 Depth 2
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: movl %r8d, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: divl %r8d
; X64-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: movl %r9d, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: divl %r9d
; X64-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: movl %edi, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: divl %edi
; X64-NEXT: xorl %edx, %edx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: movl %ecx, %eax
[X86][SSE] Regenerated known-bits test with srem->urem fix llvm-svn: 285124
2016-10-26 05:24:33 +08:00
; X64-NEXT: divl %ecx
[SelectionDAG] Ensure DAG::getZeroExtendInReg is called with a scalar type Fixes issue with rL280927 identified by Mikael Holmén llvm-svn: 281042
2016-09-09 21:31:52 +08:00
; X64-NEXT: .p2align 4, 0x90
; X64-NEXT: .LBB0_2: # %CF237
; X64-NEXT: # Parent Loop BB0_1 Depth=1
; X64-NEXT: # => This Inner Loop Header: Depth=2
; X64-NEXT: testb %sil, %sil
; X64-NEXT: jne .LBB0_2
; X64-NEXT: jmp .LBB0_1
BB:
%L5 = load i8, i8* %0
%Sl9 = select i1 true, i8 %L5, i8 undef
%B21 = udiv i8 %Sl9, -93
br label %CF
CF: ; preds = %CF246, %BB
%I40 = insertelement <4 x i8> zeroinitializer, i8 %B21, i32 1
%B41 = srem <4 x i8> %I40, %I40
br label %CF237
CF237: ; preds = %CF237, %CF
%Cmp73 = icmp ne i1 undef, undef
br i1 %Cmp73, label %CF237, label %CF246
CF246: ; preds = %CF237
%Cmp117 = icmp ult <4 x i8> %B41, undef
%E156 = extractelement <4 x i1> %Cmp117, i32 2
br label %CF
}
[X86] Add add/addc known-bits tests (D29521) llvm-svn: 294184
2017-02-06 22:06:57 +08:00
define i32 @knownbits_mask_add_lshr(i32 %a0, i32 %a1) nounwind {
; X32-LABEL: knownbits_mask_add_lshr:
; X32: # BB#0:
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: retl
;
; X64-LABEL: knownbits_mask_add_lshr:
; X64: # BB#0:
; X64-NEXT: xorl %eax, %eax
; X64-NEXT: retq
%1 = and i32 %a0, 32767
%2 = and i32 %a1, 32766
%3 = add i32 %1, %2
%4 = lshr i32 %3, 17
ret i32 %4
}
define i128 @knownbits_mask_addc_shl(i64 %a0, i64 %a1, i64 %a2) nounwind {
; X32-LABEL: knownbits_mask_addc_shl:
; X32: # BB#0:
; X32-NEXT: pushl %edi
; X32-NEXT: pushl %esi
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
; X32-NEXT: movl $-1024, %esi # imm = 0xFC00
; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
; X32-NEXT: andl %esi, %edi
; X32-NEXT: andl {{[0-9]+}}(%esp), %esi
; X32-NEXT: addl %edi, %esi
; X32-NEXT: adcl {{[0-9]+}}(%esp), %edx
; X32-NEXT: adcl $0, %ecx
; X32-NEXT: shldl $22, %edx, %ecx
; X32-NEXT: shldl $22, %esi, %edx
; X32-NEXT: movl %edx, 8(%eax)
; X32-NEXT: movl %ecx, 12(%eax)
Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits. Summary: As per title. Reviewers: bkramer, sunfish, lattner, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29521 llvm-svn: 294188
2017-02-06 22:59:06 +08:00
; X32-NEXT: movl $0, 4(%eax)
[X86] Add add/addc known-bits tests (D29521) llvm-svn: 294184
2017-02-06 22:06:57 +08:00
; X32-NEXT: movl $0, (%eax)
; X32-NEXT: popl %esi
; X32-NEXT: popl %edi
; X32-NEXT: retl $4
;
; X64-LABEL: knownbits_mask_addc_shl:
; X64: # BB#0:
; X64-NEXT: andq $-1024, %rdi # imm = 0xFC00
; X64-NEXT: andq $-1024, %rsi # imm = 0xFC00
; X64-NEXT: addq %rdi, %rsi
[DAGCombiner] Push truncate through adde when the carry isn't used. Summary: As per title. Reviewers: mkuper, spatel, bkramer, RKSimon, zvi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29528 llvm-svn: 294394
2017-02-08 08:32:36 +08:00
; X64-NEXT: adcl $0, %edx
[X86] Add add/addc known-bits tests (D29521) llvm-svn: 294184
2017-02-06 22:06:57 +08:00
; X64-NEXT: shldq $54, %rsi, %rdx
Add ADDC to SelectionDAG::computeKnownBits and ComputeNumSignBits. Summary: As per title. Reviewers: bkramer, sunfish, lattner, RKSimon Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D29521 llvm-svn: 294188
2017-02-06 22:59:06 +08:00
; X64-NEXT: xorl %eax, %eax
[X86] Add add/addc known-bits tests (D29521) llvm-svn: 294184
2017-02-06 22:06:57 +08:00
; X64-NEXT: retq
%1 = and i64 %a0, -1024
%2 = zext i64 %1 to i128
%3 = and i64 %a1, -1024
%4 = zext i64 %3 to i128
%5 = add i128 %2, %4
%6 = zext i64 %a2 to i128
%7 = shl i128 %6, 64
%8 = add i128 %5, %7
%9 = shl i128 %8, 54
ret i128 %9
}
Add test for known bits in uaddo and saddo. llvm-svn: 296255
2017-02-25 23:58:34 +08:00
define {i32, i1} @knownbits_uaddo_saddo(i64 %a0, i64 %a1) nounwind {
; X32-LABEL: knownbits_uaddo_saddo:
; X32: # BB#0:
; X32-NEXT: pushl %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
2017-05-01 03:24:09 +08:00
; X32-NEXT: movl %ecx, %edx
; X32-NEXT: addl %eax, %edx
Add test for known bits in uaddo and saddo. llvm-svn: 296255
2017-02-25 23:58:34 +08:00
; X32-NEXT: setb %bl
; X32-NEXT: testl %eax, %eax
; X32-NEXT: setns %al
; X32-NEXT: testl %ecx, %ecx
; X32-NEXT: setns %cl
; X32-NEXT: cmpb %al, %cl
; X32-NEXT: sete %al
; X32-NEXT: testl %edx, %edx
; X32-NEXT: setns %dl
; X32-NEXT: cmpb %dl, %cl
; X32-NEXT: setne %dl
; X32-NEXT: andb %al, %dl
; X32-NEXT: orb %bl, %dl
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: popl %ebx
; X32-NEXT: retl
;
; X64-LABEL: knownbits_uaddo_saddo:
; X64: # BB#0:
; X64-NEXT: shlq $32, %rdi
; X64-NEXT: shlq $32, %rsi
; X64-NEXT: addq %rdi, %rsi
[SelectionDAG] Make SelectionDAG aware of the known bits in UADDO and SADDO. Summary: As per title. This is extracted from D29872 and I threw SADDO in. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30379 llvm-svn: 297479
2017-03-11 01:06:52 +08:00
; X64-NEXT: setb %al
Add test for known bits in uaddo and saddo. llvm-svn: 296255
2017-02-25 23:58:34 +08:00
; X64-NEXT: seto %dl
[SelectionDAG] Make SelectionDAG aware of the known bits in UADDO and SADDO. Summary: As per title. This is extracted from D29872 and I threw SADDO in. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30379 llvm-svn: 297479
2017-03-11 01:06:52 +08:00
; X64-NEXT: orb %al, %dl
; X64-NEXT: xorl %eax, %eax
Add test for known bits in uaddo and saddo. llvm-svn: 296255
2017-02-25 23:58:34 +08:00
; X64-NEXT: retq
%1 = shl i64 %a0, 32
%2 = shl i64 %a1, 32
%u = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %1, i64 %2)
%uval = extractvalue {i64, i1} %u, 0
%uovf = extractvalue {i64, i1} %u, 1
%s = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %1, i64 %2)
%sval = extractvalue {i64, i1} %s, 0
%sovf = extractvalue {i64, i1} %s, 1
%sum = add i64 %uval, %sval
%3 = trunc i64 %sum to i32
%4 = or i1 %uovf, %sovf
%ret0 = insertvalue {i32, i1} undef, i32 %3, 0
%ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
ret {i32, i1} %ret1
}
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
define {i32, i1} @knownbits_usubo_ssubo(i64 %a0, i64 %a1) nounwind {
; X32-LABEL: knownbits_usubo_ssubo:
; X32: # BB#0:
; X32-NEXT: pushl %ebx
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; X32-NEXT: movl %ecx, %edx
; X32-NEXT: subl %eax, %edx
Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
2017-05-01 03:24:09 +08:00
; X32-NEXT: setb %bl
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X32-NEXT: testl %eax, %eax
; X32-NEXT: setns %al
Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
2017-05-01 03:24:09 +08:00
; X32-NEXT: testl %ecx, %ecx
; X32-NEXT: setns %cl
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X32-NEXT: cmpb %al, %cl
Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
2017-05-01 03:24:09 +08:00
; X32-NEXT: setne %al
; X32-NEXT: testl %edx, %edx
; X32-NEXT: setns %dl
; X32-NEXT: cmpb %dl, %cl
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X32-NEXT: setne %dl
Do not legalize large add with addc/adde, introduce addcarry and do it with uaddo/addcarry Summary: As per discution on how to get better codegen an large int legalization, it became clear that using a glue for the carry was preventing several desirable optimizations. Passing the carry down as a value allow for more flexibility. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: igorb, llvm-commits Differential Revision: https://reviews.llvm.org/D29872 llvm-svn: 301775
2017-05-01 03:24:09 +08:00
; X32-NEXT: andb %al, %dl
; X32-NEXT: orb %bl, %dl
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X32-NEXT: xorl %eax, %eax
; X32-NEXT: popl %ebx
; X32-NEXT: retl
;
; X64-LABEL: knownbits_usubo_ssubo:
; X64: # BB#0:
; X64-NEXT: shlq $32, %rdi
; X64-NEXT: shlq $32, %rsi
[SelectionDAG] Make SelectionDAG aware of the known bits in USUBO and SSUBO and SUBC. Summary: Depends on D30379 This improves the state of things for the sub class of operation. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30436 llvm-svn: 297482
2017-03-11 01:26:44 +08:00
; X64-NEXT: cmpq %rsi, %rdi
; X64-NEXT: setb %al
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X64-NEXT: seto %dl
[SelectionDAG] Make SelectionDAG aware of the known bits in USUBO and SSUBO and SUBC. Summary: Depends on D30379 This improves the state of things for the sub class of operation. Reviewers: jyknight, nemanjai, mkuper, spatel, RKSimon, zvi, bkramer Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30436 llvm-svn: 297482
2017-03-11 01:26:44 +08:00
; X64-NEXT: orb %al, %dl
; X64-NEXT: xorl %eax, %eax
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
; X64-NEXT: retq
%1 = shl i64 %a0, 32
%2 = shl i64 %a1, 32
%u = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %1, i64 %2)
%uval = extractvalue {i64, i1} %u, 0
%uovf = extractvalue {i64, i1} %u, 1
%s = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %1, i64 %2)
%sval = extractvalue {i64, i1} %s, 0
%sovf = extractvalue {i64, i1} %s, 1
%sum = add i64 %uval, %sval
%3 = trunc i64 %sum to i32
%4 = or i1 %uovf, %sovf
%ret0 = insertvalue {i32, i1} undef, i32 %3, 0
%ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
ret {i32, i1} %ret1
}
Add test for known bits in uaddo and saddo. llvm-svn: 296255
2017-02-25 23:58:34 +08:00
declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
Add test case for computing known bits of substraction operations. NFC llvm-svn: 296417
2017-02-28 08:15:13 +08:00
declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone