2010-01-28 14:22:43 +08:00
|
|
|
; RUN: llc < %s -march=xcore -asm-verbose=0 | FileCheck %s
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @ashr(i32 %a, i32 %b) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = ashr i32 %a, %b
|
|
|
|
ret i32 %1
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: ashr:
|
2009-10-08 23:38:17 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, r1
|
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @ashri1(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = ashr i32 %a, 24
|
|
|
|
ret i32 %1
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: ashri1:
|
2009-10-08 23:38:17 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 24
|
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @ashri2(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = ashr i32 %a, 31
|
|
|
|
ret i32 %1
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: ashri2:
|
2009-10-08 23:38:17 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 32
|
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @f1(i32 %a) nounwind nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = icmp slt i32 %a, 0
|
|
|
|
br i1 %1, label %less, label %not_less
|
|
|
|
less:
|
|
|
|
ret i32 10
|
|
|
|
not_less:
|
|
|
|
ret i32 17
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f1:
|
2009-10-08 23:38:17 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 32
|
2012-04-16 21:49:17 +08:00
|
|
|
; CHECK-NEXT: bt r0
|
2009-10-08 23:38:17 +08:00
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @f2(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = icmp sge i32 %a, 0
|
|
|
|
br i1 %1, label %greater, label %not_greater
|
|
|
|
greater:
|
|
|
|
ret i32 10
|
|
|
|
not_greater:
|
|
|
|
ret i32 17
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f2:
|
2009-10-08 23:38:17 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 32
|
|
|
|
; CHECK-NEXT: bt r0
|
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @f3(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = icmp slt i32 %a, 0
|
|
|
|
%2 = select i1 %1, i32 10, i32 17
|
|
|
|
ret i32 %2
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f3:
|
Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-21 06:52:00 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 32
|
2012-04-16 21:49:17 +08:00
|
|
|
; CHECK-NEXT: bt r0
|
|
|
|
; CHECK-NEXT: ldc r0, 17
|
|
|
|
; CHECK: ldc r0, 10
|
2009-10-08 23:38:17 +08:00
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @f4(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = icmp sge i32 %a, 0
|
|
|
|
%2 = select i1 %1, i32 10, i32 17
|
|
|
|
ret i32 %2
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f4:
|
Enable machine sinking critical edge splitting. e.g.
define double @foo(double %x, double %y, i1 %c) nounwind {
%a = fdiv double %x, 3.2
%z = select i1 %c, double %a, double %y
ret double %z
}
Was:
_foo:
divsd LCPI0_0(%rip), %xmm0
testb $1, %dil
jne LBB0_2
movaps %xmm1, %xmm0
LBB0_2:
ret
Now:
_foo:
testb $1, %dil
je LBB0_2
divsd LCPI0_0(%rip), %xmm0
ret
LBB0_2:
movaps %xmm1, %xmm0
ret
This avoids the divsd when early exit is taken.
rdar://8454886
llvm-svn: 114372
2010-09-21 06:52:00 +08:00
|
|
|
; CHECK-NEXT: ashr r0, r0, 32
|
2012-04-16 21:49:17 +08:00
|
|
|
; CHECK-NEXT: bt r0
|
|
|
|
; CHECK-NEXT: ldc r0, 10
|
|
|
|
; CHECK: ldc r0, 17
|
2009-10-08 23:38:17 +08:00
|
|
|
|
2013-11-13 18:19:31 +08:00
|
|
|
define i32 @f5(i32 %a) nounwind {
|
2009-10-08 23:38:17 +08:00
|
|
|
%1 = icmp sge i32 %a, 0
|
|
|
|
%2 = zext i1 %1 to i32
|
|
|
|
ret i32 %2
|
|
|
|
}
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: f5:
|
[DAGCombiner] extend(ifpositive(X)) -> shift-right (not X)
This is almost the same as an existing IR canonicalization in instcombine,
so I'm assuming this is a good early generic DAG combine too.
The motivation comes from reduced bit-hacking for select-of-constants in IR
after rL331486. We want to restore that functionality in the DAG as noted in
the commit comments for that change and the llvm-dev discussion here:
http://lists.llvm.org/pipermail/llvm-dev/2018-July/124433.html
The PPC and AArch tests show that those targets are already doing something
similar. x86 will be neutral in the minimal case and generally better when
this pattern is extended with other ops as shown in the signbit-shift.ll tests.
Note the asymmetry: we don't include the (extend (ifneg X)) transform because
it already exists in SimplifySelectCC(), and that is verified in the later
unchanged tests in the signbit-shift.ll files. Without the 'not' op, the
general transform to use a shift is always a win because that's a single
instruction.
Alive proofs:
https://rise4fun.com/Alive/ysli
Name: if pos, get -1
%c = icmp sgt i16 %x, -1
%r = sext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = ashr i16 %n, 15
Name: if pos, get 1
%c = icmp sgt i16 %x, -1
%r = zext i1 %c to i16
=>
%n = xor i16 %x, -1
%r = lshr i16 %n, 15
Differential Revision: https://reviews.llvm.org/D48970
llvm-svn: 337130
2018-07-16 00:27:07 +08:00
|
|
|
; CHECK-NEXT: not r0, r0
|
|
|
|
; CHECK-NEXT: mkmsk r1, 5
|
|
|
|
; CHECK-NEXT: shr r0, r0, r1
|