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llvm-project/llvm/test/CodeGen/ARM/arm-modifier.ll

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Re-commit: Demote EmitRawText call in AsmPrinter::EmitInlineAsm() and remove hasRawTextSupport() call Summary: AsmPrinter::EmitInlineAsm() will no longer use the EmitRawText() call for targets with mature MC support. Such targets will always parse the inline assembly (even when emitting assembly). Targets without mature MC support continue to use EmitRawText() for assembly output. The hasRawTextSupport() check in AsmPrinter::EmitInlineAsm() has been replaced with MCAsmInfo::UseIntegratedAs which when true, causes the integrated assembler to parse inline assembly (even when emitting assembly output). UseIntegratedAs is set to true for targets that consider any failure to parse valid assembly to be a bug. Target specific subclasses generally enable the integrated assembler in their constructor. The default value can be overridden with -no-integrated-as. All tests that rely on inline assembly supporting invalid assembly (for example, those that use mnemonics such as 'foo' or 'hello world') have been updated to disable the integrated assembler. Changes since review (and last commit attempt): - Fixed test failures that were missed due to configuration of local build. (fixes crash.ll and a couple others). - Fixed tests that happened to pass because the local build was on X86 (should fix 2007-12-17-InvokeAsm.ll) - mature-mc-support.ll's should no longer require all targets to be compiled. (should fix ARM and PPC buildbots) - Object output (-filetype=obj and similar) now forces the integrated assembler to be enabled regardless of default setting or -no-integrated-as. (should fix SystemZ buildbots) Reviewers: rafael Reviewed By: rafael CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D2686 llvm-svn: 201333
2014-02-13 22:44:26 +08:00
; RUN: llc < %s -march=arm -mattr=+vfp2 -no-integrated-as | FileCheck %s
Add support for the arm 'y' asm modifier. Fixes part of rdar://9444657 llvm-svn: 132011
2011-05-25 06:10:34 +08:00
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
define i32 @foo(float %scale, float %scale2) nounwind {
Add support for the arm 'y' asm modifier. Fixes part of rdar://9444657 llvm-svn: 132011
2011-05-25 06:10:34 +08:00
entry:
%scale.addr = alloca float, align 4
%scale2.addr = alloca float, align 4
store float %scale, float* %scale.addr, align 4
store float %scale2, float* %scale2.addr, align 4
%tmp = load float* %scale.addr, align 4
%tmp1 = load float* %scale2.addr, align 4
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind
Add support for the arm 'y' asm modifier. Fixes part of rdar://9444657 llvm-svn: 132011
2011-05-25 06:10:34 +08:00
ret i32 0
}
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
define void @f0() nounwind {
Implement the immediate part of the 'B' modifier. Part of rdar://9119939 llvm-svn: 132023
2011-05-25 07:15:43 +08:00
entry:
; CHECK: f0
; CHECK: .word -1
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
call void asm sideeffect ".word ${0:B} \0A\09", "i"(i32 0) nounwind
Implement the immediate part of the 'B' modifier. Part of rdar://9119939 llvm-svn: 132023
2011-05-25 07:15:43 +08:00
ret void
}
Implement the arm 'L' asm modifier. Part of rdar://9119939 llvm-svn: 132024
2011-05-25 07:27:13 +08:00
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
define void @f1() nounwind {
Implement the arm 'L' asm modifier. Part of rdar://9119939 llvm-svn: 132024
2011-05-25 07:27:13 +08:00
entry:
; CHECK: f1
; CHECK: .word 65535
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind
Implement the arm 'L' asm modifier. Part of rdar://9119939 llvm-svn: 132024
2011-05-25 07:27:13 +08:00
ret void
}
Implement the 'm' modifier. Note that it only works for memory operands. Part of rdar://9119939 llvm-svn: 132081
2011-05-26 04:51:58 +08:00
@f2_ptr = internal global i32* @f2_var, align 4
@f2_var = external global i32
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
define void @f2() nounwind {
Implement the 'm' modifier. Note that it only works for memory operands. Part of rdar://9119939 llvm-svn: 132081
2011-05-26 04:51:58 +08:00
entry:
; CHECK: f2
; CHECK: ldr r0, [r{{[0-9]+}}]
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(i32** @f2_ptr) nounwind
ret void
}
@f3_ptr = internal global i64* @f3_var, align 4
@f3_var = external global i64
@f3_var2 = external global i64
define void @f3() nounwind {
entry:
; CHECK: f3
Allow lr in the register options here. llvm-svn: 133935
2011-06-28 04:31:01 +08:00
; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
Implement the 'M' output modifier for arm inline asm. This is fairly register allocation dependent and will occasionally break. WIP in the register allocator to model paired/etc registers. rdar://9119939 llvm-svn: 132242
2011-05-28 09:40:44 +08:00
%tmp = load i64* @f3_var, align 4
%tmp1 = load i64* @f3_var2, align 4
%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
store i64 %0, i64* @f3_var, align 4
%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind
store i64 %1, i64* @f3_var, align 4
Implement the 'm' modifier. Note that it only works for memory operands. Part of rdar://9119939 llvm-svn: 132081
2011-05-26 04:51:58 +08:00
ret void
}
Add support for the %H output modifier. Patch by Weiming Zhao. llvm-svn: 161768
2012-08-14 02:18:52 +08:00
define i64 @f4(i64* %val) nounwind {
entry:
Update to more CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change. All changes were made by the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" grep -q "^; *RUN: *llc.*debug" $NAME && continue grep -q "^; *RUN:.*llvm-objdump" $NAME && continue grep -q "^; *RUN: *opt.*" $NAME && continue TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\([A-Za-z0-9_-]*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC[:]* *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME done This script catches a superset of the cases caught by the script associated with commit r186280. It initially found some false positives due to unusual constructs in a minority of tests; all such cases were disambiguated first in commit r186621. llvm-svn: 186624
2013-07-19 06:47:09 +08:00
;CHECK-LABEL: f4:
Re-apply r175088 for bug fix 13622: Add paired register support for inline asm with 64-bit data on ARM Update test case to use -mtriple=arm-linux-gnueabi llvm-svn: 175186
2013-02-15 02:10:21 +08:00
;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
Add support for the %H output modifier. Patch by Weiming Zhao. llvm-svn: 161768
2012-08-14 02:18:52 +08:00
%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
ret i64 %0
}
PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm. In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. llvm-svn: 185688
2013-07-05 18:19:40 +08:00
Add a comment to this change, requested by Eric Christopher. llvm-svn: 185853
2013-07-09 03:52:51 +08:00
; PR16490
PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm. In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. llvm-svn: 185688
2013-07-05 18:19:40 +08:00
define void @f5(i64 %__pu_val) {
call void asm sideeffect "$1", "r,i"(i64 %__pu_val, i32 -14)
ret void
}