2012-02-18 20:03:15 +08:00
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//===-- X86InstrInfo.h - X86 Instruction Information ------------*- C++ -*-===//
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2005-04-22 07:38:14 +08:00
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//
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2003-10-21 23:17:13 +08:00
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-04-22 07:38:14 +08:00
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//
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2003-10-21 23:17:13 +08:00
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//===----------------------------------------------------------------------===//
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2002-10-26 06:55:53 +08:00
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//
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2003-01-15 06:00:31 +08:00
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// This file contains the X86 implementation of the TargetInstrInfo class.
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2002-10-26 06:55:53 +08:00
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86INSTRUCTIONINFO_H
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#define X86INSTRUCTIONINFO_H
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2008-04-17 04:10:13 +08:00
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#include "X86.h"
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2002-10-26 06:55:53 +08:00
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#include "X86RegisterInfo.h"
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2009-01-06 01:59:02 +08:00
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#include "llvm/ADT/DenseMap.h"
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2012-03-18 02:46:09 +08:00
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#include "llvm/Target/TargetInstrInfo.h"
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2002-10-26 06:55:53 +08:00
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2011-07-02 01:57:27 +08:00
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#define GET_INSTRINFO_HEADER
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#include "X86GenInstrInfo.inc"
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2003-11-12 06:41:34 +08:00
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namespace llvm {
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2006-09-08 14:48:29 +08:00
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class X86RegisterInfo;
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2006-05-31 05:45:53 +08:00
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class X86TargetMachine;
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2003-11-12 06:41:34 +08:00
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2006-10-21 01:42:20 +08:00
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namespace X86 {
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// X86 specific condition code. These correspond to X86_*_COND in
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// X86InstrInfo.td. They must be kept in synch.
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enum CondCode {
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COND_A = 0,
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COND_AE = 1,
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COND_B = 2,
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COND_BE = 3,
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COND_E = 4,
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COND_G = 5,
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COND_GE = 6,
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COND_L = 7,
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COND_LE = 8,
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COND_NE = 9,
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COND_NO = 10,
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COND_NP = 11,
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COND_NS = 12,
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2009-01-07 08:15:08 +08:00
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COND_O = 13,
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COND_P = 14,
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COND_S = 15,
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Optimized FCMP_OEQ and FCMP_UNE for x86.
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 11:29:32 +08:00
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// Artificial condition codes. These are used by AnalyzeBranch
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// to indicate a block terminated with two conditional branches to
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// the same location. This occurs in code using FCMP_OEQ or FCMP_UNE,
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// which can't be represented on x86 with a single condition. These
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// are never used in MachineInstrs.
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COND_NE_OR_P,
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COND_NP_OR_E,
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2006-10-21 01:42:20 +08:00
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COND_INVALID
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};
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2011-03-05 14:31:54 +08:00
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2006-10-21 01:42:20 +08:00
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// Turn condition code into conditional branch opcode.
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unsigned GetCondBranchFromCond(CondCode CC);
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2011-03-05 14:31:54 +08:00
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2006-10-21 13:52:40 +08:00
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/// GetOppositeBranchCondition - Return the inverse of the specified cond,
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/// e.g. turning COND_E to COND_NE.
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CondCode GetOppositeBranchCondition(X86::CondCode CC);
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2011-07-26 02:43:53 +08:00
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} // end namespace X86;
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2006-10-21 13:52:40 +08:00
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2009-07-10 14:06:17 +08:00
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2009-07-10 14:29:59 +08:00
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/// isGlobalStubReference - Return true if the specified TargetFlag operand is
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2009-07-10 14:06:17 +08:00
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/// a reference to a stub for a global, not the global itself.
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2009-07-10 14:29:59 +08:00
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inline static bool isGlobalStubReference(unsigned char TargetFlag) {
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switch (TargetFlag) {
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2009-07-10 14:06:17 +08:00
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case X86II::MO_DLLIMPORT: // dllimport stub.
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case X86II::MO_GOTPCREL: // rip-relative GOT reference.
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case X86II::MO_GOT: // normal GOT reference.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_NONLAZY: // Normal $non_lazy_ptr ref.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Hidden $non_lazy_ptr ref.
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return true;
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default:
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return false;
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}
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}
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2009-07-10 15:33:30 +08:00
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/// isGlobalRelativeToPICBase - Return true if the specified global value
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/// reference is relative to a 32-bit PIC base (X86ISD::GlobalBaseReg). If this
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/// is true, the addressing mode has the PIC base register added in (e.g. EBX).
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inline static bool isGlobalRelativeToPICBase(unsigned char TargetFlag) {
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switch (TargetFlag) {
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case X86II::MO_GOTOFF: // isPICStyleGOT: local global.
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case X86II::MO_GOT: // isPICStyleGOT: other global.
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case X86II::MO_PIC_BASE_OFFSET: // Darwin local global.
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case X86II::MO_DARWIN_NONLAZY_PIC_BASE: // Darwin/32 external global.
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case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: // Darwin/32 hidden global.
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2010-06-03 12:07:48 +08:00
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case X86II::MO_TLVP: // ??? Pretty sure..
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2009-07-10 15:33:30 +08:00
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return true;
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default:
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return false;
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}
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}
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2011-03-05 14:31:54 +08:00
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2008-06-28 19:07:54 +08:00
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inline static bool isScale(const MachineOperand &MO) {
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2008-10-03 23:45:36 +08:00
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return MO.isImm() &&
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2008-06-28 19:07:54 +08:00
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(MO.getImm() == 1 || MO.getImm() == 2 ||
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MO.getImm() == 4 || MO.getImm() == 8);
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}
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2009-04-09 05:14:34 +08:00
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inline static bool isLeaMem(const MachineInstr *MI, unsigned Op) {
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2008-10-03 23:45:36 +08:00
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if (MI->getOperand(Op).isFI()) return true;
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2008-06-28 19:07:54 +08:00
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return Op+4 <= MI->getNumOperands() &&
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2008-10-03 23:45:36 +08:00
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MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isReg() &&
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(MI->getOperand(Op+3).isImm() ||
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MI->getOperand(Op+3).isGlobal() ||
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MI->getOperand(Op+3).isCPI() ||
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MI->getOperand(Op+3).isJTI());
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2008-06-28 19:07:54 +08:00
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}
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2009-04-09 05:14:34 +08:00
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inline static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFI()) return true;
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return Op+5 <= MI->getNumOperands() &&
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MI->getOperand(Op+4).isReg() &&
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isLeaMem(MI, Op);
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}
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2011-07-02 01:57:27 +08:00
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class X86InstrInfo : public X86GenInstrInfo {
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2006-05-31 05:45:53 +08:00
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X86TargetMachine &TM;
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2002-10-26 06:55:53 +08:00
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const X86RegisterInfo RI;
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2011-03-05 14:31:54 +08:00
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2008-01-07 09:35:02 +08:00
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/// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1,
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/// RegOp2MemOpTable2 - Load / store folding opcode maps.
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///
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* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
llvm-svn: 139311
2011-09-09 02:35:57 +08:00
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typedef DenseMap<unsigned,
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std::pair<unsigned, unsigned> > RegOp2MemOpTableType;
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RegOp2MemOpTableType RegOp2MemOpTable2Addr;
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RegOp2MemOpTableType RegOp2MemOpTable0;
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RegOp2MemOpTableType RegOp2MemOpTable1;
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RegOp2MemOpTableType RegOp2MemOpTable2;
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2011-03-05 14:31:54 +08:00
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2008-01-07 09:35:02 +08:00
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/// MemOp2RegOpTable - Load / store unfolding opcode map.
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///
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* Combines Alignment, AuxInfo, and TB_NOT_REVERSABLE flag into a
single field (Flags), which is a bitwise OR of items from the TB_*
enum. This makes it easier to add new information in the future.
* Gives every static array an equivalent layout: { RegOp, MemOp, Flags }
* Adds a helper function, AddTableEntry, to avoid duplication of the
insertion code.
* Renames TB_NOT_REVERSABLE to TB_NO_REVERSE.
* Adds TB_NO_FORWARD, which is analogous to TB_NO_REVERSE, except that
it prevents addition of the Reg->Mem entry. (This is going to be used
by Native Client, in the next CL).
Patch by David Meyer
llvm-svn: 139311
2011-09-09 02:35:57 +08:00
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typedef DenseMap<unsigned,
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std::pair<unsigned, unsigned> > MemOp2RegOpTableType;
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MemOp2RegOpTableType MemOp2RegOpTable;
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void AddTableEntry(RegOp2MemOpTableType &R2MTable,
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MemOp2RegOpTableType &M2RTable,
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unsigned RegOp, unsigned MemOp, unsigned Flags);
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2010-03-26 01:25:00 +08:00
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2002-10-26 06:55:53 +08:00
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public:
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2008-03-26 06:06:05 +08:00
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explicit X86InstrInfo(X86TargetMachine &tm);
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2002-10-26 06:55:53 +08:00
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2003-01-15 06:00:31 +08:00
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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2002-10-26 06:55:53 +08:00
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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2008-05-14 09:58:56 +08:00
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virtual const X86RegisterInfo &getRegisterInfo() const { return RI; }
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2002-10-26 06:55:53 +08:00
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2010-01-13 08:30:23 +08:00
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/// isCoalescableExtInstr - Return true if the instruction is a "coalescable"
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/// extension instruction. That is, it's like a copy where it's legal for the
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/// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns
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/// true, then it's expected the pre-extension value is available as a subreg
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/// of the result register. This also returns the sub-register index in
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/// SubIdx.
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virtual bool isCoalescableExtInstr(const MachineInstr &MI,
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unsigned &SrcReg, unsigned &DstReg,
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unsigned &SubIdx) const;
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2010-01-12 08:09:37 +08:00
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2008-11-19 03:49:32 +08:00
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unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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2009-11-13 08:29:53 +08:00
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/// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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2009-11-13 04:55:29 +08:00
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2008-11-19 03:49:32 +08:00
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unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
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2009-11-13 08:29:53 +08:00
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/// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
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/// stack locations as well. This uses a heuristic so it isn't
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/// reliable for correctness.
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unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
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int &FrameIndex) const;
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2008-04-01 04:40:39 +08:00
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2009-10-10 08:34:18 +08:00
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bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
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AliasAnalysis *AA) const;
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2008-04-01 04:40:39 +08:00
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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2009-07-16 17:20:10 +08:00
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unsigned DestReg, unsigned SubIdx,
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2009-11-14 10:55:43 +08:00
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const MachineInstr *Orig,
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2010-06-03 06:47:25 +08:00
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const TargetRegisterInfo &TRI) const;
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2008-04-01 04:40:39 +08:00
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2005-01-02 10:37:07 +08:00
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/// convertToThreeAddress - This method must be implemented by targets that
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/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
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/// may be able to convert a two-address instruction into a true
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/// three-address instruction on demand. This allows the X86 target (for
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/// example) to convert ADD and SHL instructions into LEA instructions if they
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/// would require register copies due to two-addressness.
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///
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/// This method returns a null pointer if the transformation cannot be
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/// performed, otherwise it returns the new instruction.
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///
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2006-12-02 05:52:58 +08:00
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virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
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MachineBasicBlock::iterator &MBBI,
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2008-07-03 07:41:07 +08:00
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LiveVariables *LV) const;
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2005-01-02 10:37:07 +08:00
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 15:11:01 +08:00
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/// commuteInstruction - We have a few instructions that must be hacked on to
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/// commute them.
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///
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2008-06-16 15:33:11 +08:00
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virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
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Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 15:11:01 +08:00
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2006-10-21 01:42:20 +08:00
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// Branch analysis.
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2007-06-15 06:03:45 +08:00
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virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
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2006-10-21 01:42:20 +08:00
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virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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2009-02-09 15:14:22 +08:00
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const;
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2007-05-18 08:18:17 +08:00
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virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
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virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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2010-06-18 06:43:56 +08:00
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const;
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2010-07-09 03:46:25 +08:00
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virtual void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const;
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2008-01-02 05:11:32 +08:00
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virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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2010-05-07 03:06:44 +08:00
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const;
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2008-01-02 05:11:32 +08:00
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virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
|
2009-10-10 02:10:05 +08:00
|
|
|
MachineInstr::mmo_iterator MMOBegin,
|
|
|
|
MachineInstr::mmo_iterator MMOEnd,
|
2008-01-02 05:11:32 +08:00
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
|
|
|
|
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|
|
|
MachineBasicBlock::iterator MI,
|
|
|
|
unsigned DestReg, int FrameIndex,
|
2010-05-07 03:06:44 +08:00
|
|
|
const TargetRegisterClass *RC,
|
|
|
|
const TargetRegisterInfo *TRI) const;
|
2008-01-02 05:11:32 +08:00
|
|
|
|
|
|
|
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
|
|
|
SmallVectorImpl<MachineOperand> &Addr,
|
|
|
|
const TargetRegisterClass *RC,
|
2009-10-10 02:10:05 +08:00
|
|
|
MachineInstr::mmo_iterator MMOBegin,
|
|
|
|
MachineInstr::mmo_iterator MMOEnd,
|
2008-01-02 05:11:32 +08:00
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
2011-09-29 13:10:54 +08:00
|
|
|
|
|
|
|
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
|
|
|
|
|
2010-04-26 15:38:55 +08:00
|
|
|
virtual
|
|
|
|
MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF,
|
2010-04-29 09:13:30 +08:00
|
|
|
int FrameIx, uint64_t Offset,
|
2010-04-26 15:38:55 +08:00
|
|
|
const MDNode *MDPtr,
|
|
|
|
DebugLoc DL) const;
|
|
|
|
|
2008-01-07 09:35:02 +08:00
|
|
|
/// foldMemoryOperand - If this target supports it, fold a load or store of
|
|
|
|
/// the specified stack slot into the specified machine instruction for the
|
|
|
|
/// specified operand(s). If this is possible, the target should perform the
|
|
|
|
/// folding and return true, otherwise it should return false. If it folds
|
|
|
|
/// the instruction, it is likely that the MachineInstruction the iterator
|
|
|
|
/// references has been changed.
|
2008-12-04 02:43:12 +08:00
|
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
|
|
int FrameIndex) const;
|
2008-01-07 09:35:02 +08:00
|
|
|
|
|
|
|
/// foldMemoryOperand - Same as the previous version except it allows folding
|
|
|
|
/// of any load and store from / to any address, not just from a specific
|
|
|
|
/// stack slot.
|
2008-12-04 02:43:12 +08:00
|
|
|
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
const SmallVectorImpl<unsigned> &Ops,
|
|
|
|
MachineInstr* LoadMI) const;
|
2008-01-07 09:35:02 +08:00
|
|
|
|
|
|
|
/// canFoldMemoryOperand - Returns true if the specified load / store is
|
|
|
|
/// folding is possible.
|
2008-10-16 09:49:15 +08:00
|
|
|
virtual bool canFoldMemoryOperand(const MachineInstr*,
|
|
|
|
const SmallVectorImpl<unsigned> &) const;
|
2008-01-07 09:35:02 +08:00
|
|
|
|
|
|
|
/// unfoldMemoryOperand - Separate a single instruction which folded a load or
|
|
|
|
/// a store or a load and a store into two or more instruction. If this is
|
|
|
|
/// possible, returns true as well as the new instructions by reference.
|
|
|
|
virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
|
|
|
|
unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
|
|
|
|
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
|
|
|
|
|
|
|
virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
|
|
|
SmallVectorImpl<SDNode*> &NewNodes) const;
|
|
|
|
|
|
|
|
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
|
|
|
/// instruction after load / store are unfolded from an instruction of the
|
|
|
|
/// specified opcode. It returns zero if the specified unfolding is not
|
2009-10-31 06:18:41 +08:00
|
|
|
/// possible. If LoadRegIndex is non-null, it is filled in with the operand
|
|
|
|
/// index of the operand which will hold the register holding the loaded
|
|
|
|
/// value.
|
2008-01-07 09:35:02 +08:00
|
|
|
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
2009-10-31 06:18:41 +08:00
|
|
|
bool UnfoldLoad, bool UnfoldStore,
|
|
|
|
unsigned *LoadRegIndex = 0) const;
|
2011-03-05 14:31:54 +08:00
|
|
|
|
2010-01-22 11:34:51 +08:00
|
|
|
/// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
|
|
|
|
/// to determine if two loads are loading from the same base address. It
|
|
|
|
/// should only return true if the base pointers are the same and the
|
|
|
|
/// only differences between the two addresses are the offset. It also returns
|
|
|
|
/// the offsets by reference.
|
|
|
|
virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
|
|
|
|
int64_t &Offset1, int64_t &Offset2) const;
|
|
|
|
|
|
|
|
/// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
|
2011-04-15 13:18:47 +08:00
|
|
|
/// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
|
2010-01-22 11:34:51 +08:00
|
|
|
/// be scheduled togther. On some targets if two loads are loading from
|
|
|
|
/// addresses in the same cache line, it's better if they are scheduled
|
|
|
|
/// together. This function takes two integers that represent the load offsets
|
|
|
|
/// from the common base address. It returns true if it decides it's desirable
|
|
|
|
/// to schedule the two loads together. "NumLoads" is the number of loads that
|
|
|
|
/// have already been scheduled after Load1.
|
|
|
|
virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
|
|
|
int64_t Offset1, int64_t Offset2,
|
|
|
|
unsigned NumLoads) const;
|
|
|
|
|
2010-04-27 07:37:21 +08:00
|
|
|
virtual void getNoopForMachoTarget(MCInst &NopInst) const;
|
|
|
|
|
2008-08-15 06:49:33 +08:00
|
|
|
virtual
|
|
|
|
bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
|
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
llvm-svn: 19686
2005-01-19 15:11:01 +08:00
|
|
|
|
2009-02-07 01:17:30 +08:00
|
|
|
/// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
|
|
|
|
/// instruction that defines the specified register class.
|
|
|
|
bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
|
2008-10-27 15:14:50 +08:00
|
|
|
|
2010-02-06 06:10:22 +08:00
|
|
|
static bool isX86_64ExtendedReg(const MachineOperand &MO) {
|
|
|
|
if (!MO.isReg()) return false;
|
2011-07-26 02:43:53 +08:00
|
|
|
return X86II::isX86_64ExtendedReg(MO.getReg());
|
2010-02-06 06:10:22 +08:00
|
|
|
}
|
2008-04-17 04:10:13 +08:00
|
|
|
|
2008-09-30 08:58:23 +08:00
|
|
|
/// getGlobalBaseReg - Return a virtual register initialized with the
|
|
|
|
/// the global base register value. Output instructions required to
|
|
|
|
/// initialize the register in the function entry block, if necessary.
|
2008-09-24 02:22:58 +08:00
|
|
|
///
|
2008-09-30 08:58:23 +08:00
|
|
|
unsigned getGlobalBaseReg(MachineFunction *MF) const;
|
2008-09-24 02:22:58 +08:00
|
|
|
|
2011-09-28 06:57:18 +08:00
|
|
|
std::pair<uint16_t, uint16_t>
|
|
|
|
getExecutionDomain(const MachineInstr *MI) const;
|
2010-03-30 07:24:21 +08:00
|
|
|
|
2011-09-28 06:57:18 +08:00
|
|
|
void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
|
2010-03-26 01:25:00 +08:00
|
|
|
|
2011-11-15 09:15:30 +08:00
|
|
|
unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
|
|
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
|
|
|
|
const TargetRegisterInfo *TRI) const;
|
|
|
|
|
implement rdar://6653118 - fastisel should fold loads where possible.
Since mem2reg isn't run at -O0, we get a ton of reloads from the stack,
for example, before, this code:
int foo(int x, int y, int z) {
return x+y+z;
}
used to compile into:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
movl 4(%rsp), %esi
addl %edx, %esi
movl (%rsp), %edx
addl %esi, %edx
movl %edx, %eax
addq $12, %rsp
ret
Now we produce:
_foo: ## @foo
subq $12, %rsp
movl %edi, 8(%rsp)
movl %esi, 4(%rsp)
movl %edx, (%rsp)
movl 8(%rsp), %edx
addl 4(%rsp), %edx ## Folded load
addl (%rsp), %edx ## Folded load
movl %edx, %eax
addq $12, %rsp
ret
Fewer instructions and less register use = faster compiles.
llvm-svn: 113102
2010-09-05 10:18:34 +08:00
|
|
|
MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
|
|
|
|
MachineInstr* MI,
|
|
|
|
unsigned OpNum,
|
|
|
|
const SmallVectorImpl<MachineOperand> &MOs,
|
|
|
|
unsigned Size, unsigned Alignment) const;
|
2010-10-20 02:58:51 +08:00
|
|
|
|
2011-03-05 16:00:22 +08:00
|
|
|
bool isHighLatencyDef(int opc) const;
|
|
|
|
|
2010-10-20 02:58:51 +08:00
|
|
|
bool hasHighOperandLatency(const InstrItineraryData *ItinData,
|
|
|
|
const MachineRegisterInfo *MRI,
|
|
|
|
const MachineInstr *DefMI, unsigned DefIdx,
|
|
|
|
const MachineInstr *UseMI, unsigned UseIdx) const;
|
2011-03-05 14:31:54 +08:00
|
|
|
|
2008-01-07 09:35:02 +08:00
|
|
|
private:
|
2009-12-11 14:01:48 +08:00
|
|
|
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
|
|
|
|
MachineFunction::iterator &MFI,
|
|
|
|
MachineBasicBlock::iterator &MBBI,
|
|
|
|
LiveVariables *LV) const;
|
|
|
|
|
2009-11-13 04:55:29 +08:00
|
|
|
/// isFrameOperand - Return true and the FrameIndex if the specified
|
|
|
|
/// operand and follow operands form a reference to the stack frame.
|
|
|
|
bool isFrameOperand(const MachineInstr *MI, unsigned int Op,
|
|
|
|
int &FrameIndex) const;
|
2002-10-26 06:55:53 +08:00
|
|
|
};
|
|
|
|
|
2003-11-12 06:41:34 +08:00
|
|
|
} // End llvm namespace
|
|
|
|
|
2002-10-26 06:55:53 +08:00
|
|
|
#endif
|