2012-02-18 20:03:15 +08:00
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//===-- HexagonTargetMachine.cpp - Define TargetMachine for Hexagon -------===//
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2011-12-13 05:14:40 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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2012-02-18 20:03:15 +08:00
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// Implements the info about Hexagon target spec.
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2011-12-13 05:14:40 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "HexagonTargetMachine.h"
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#include "Hexagon.h"
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#include "HexagonISelLowering.h"
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2012-09-04 22:49:56 +08:00
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#include "HexagonMachineScheduler.h"
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2013-05-08 03:53:00 +08:00
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#include "HexagonTargetObjectFile.h"
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2011-12-13 05:14:40 +08:00
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#include "llvm/CodeGen/Passes.h"
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2013-01-02 19:36:10 +08:00
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#include "llvm/IR/Module.h"
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2011-12-13 05:14:40 +08:00
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#include "llvm/PassManager.h"
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2012-02-06 18:19:29 +08:00
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#include "llvm/Support/CommandLine.h"
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2011-12-13 05:14:40 +08:00
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#include "llvm/Support/TargetRegistry.h"
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2012-12-04 00:50:05 +08:00
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#include "llvm/Transforms/IPO/PassManagerBuilder.h"
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#include "llvm/Transforms/Scalar.h"
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2011-12-13 05:14:40 +08:00
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using namespace llvm;
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2013-05-07 05:25:45 +08:00
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static cl:: opt<bool> DisableHardwareLoops("disable-hexagon-hwloops",
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cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target"));
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2011-12-13 05:14:40 +08:00
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2013-05-07 05:25:45 +08:00
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static cl::opt<bool> DisableHexagonMISched("disable-hexagon-misched",
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon MI Scheduling"));
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2012-09-04 22:49:56 +08:00
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2013-03-27 19:14:24 +08:00
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static cl::opt<bool> DisableHexagonCFGOpt("disable-hexagon-cfgopt",
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2013-05-07 05:25:45 +08:00
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cl::Hidden, cl::ZeroOrMore, cl::init(false),
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cl::desc("Disable Hexagon CFG Optimization"));
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2013-03-27 19:14:24 +08:00
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2011-12-13 05:14:40 +08:00
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/// HexagonTargetMachineModule - Note that this is used on hosts that
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/// cannot link in a library unless there are references into the
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/// library. In particular, it seems that it is not possible to get
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/// things to work on Win32 without this. Though it is unused, do not
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/// remove it.
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extern "C" int HexagonTargetMachineModule;
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int HexagonTargetMachineModule = 0;
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extern "C" void LLVMInitializeHexagonTarget() {
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// Register the target.
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RegisterTargetMachine<HexagonTargetMachine> X(TheHexagonTarget);
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}
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2012-09-04 22:49:56 +08:00
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static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) {
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2014-04-22 04:32:32 +08:00
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return new VLIWMachineScheduler(C, make_unique<ConvergingVLIWScheduler>());
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2012-09-04 22:49:56 +08:00
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}
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static MachineSchedRegistry
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SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler",
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createVLIWMachineSched);
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2011-12-13 05:14:40 +08:00
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/// HexagonTargetMachine ctor - Create an ILP32 architecture model.
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///
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/// Hexagon_TODO: Do I need an aggregate alignment?
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///
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HexagonTargetMachine::HexagonTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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2012-03-17 17:24:09 +08:00
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const TargetOptions &Options,
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2011-12-13 05:14:40 +08:00
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Reloc::Model RM,
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CodeModel::Model CM,
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CodeGenOpt::Level OL)
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: LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
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2014-01-04 03:21:54 +08:00
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DL("e-m:e-p:32:32-i1:32-i64:64-a:0-n32") ,
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2011-12-17 03:08:59 +08:00
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Subtarget(TT, CPU, FS), InstrInfo(Subtarget), TLInfo(*this),
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2011-12-13 05:14:40 +08:00
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TSInfo(*this),
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FrameLowering(Subtarget),
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Switch TargetTransformInfo from an immutable analysis pass that requires
a TargetMachine to construct (and thus isn't always available), to an
analysis group that supports layered implementations much like
AliasAnalysis does. This is a pretty massive change, with a few parts
that I was unable to easily separate (sorry), so I'll walk through it.
The first step of this conversion was to make TargetTransformInfo an
analysis group, and to sink the nonce implementations in
ScalarTargetTransformInfo and VectorTargetTranformInfo into
a NoTargetTransformInfo pass. This allows other passes to add a hard
requirement on TTI, and assume they will always get at least on
implementation.
The TargetTransformInfo analysis group leverages the delegation chaining
trick that AliasAnalysis uses, where the base class for the analysis
group delegates to the previous analysis *pass*, allowing all but tho
NoFoo analysis passes to only implement the parts of the interfaces they
support. It also introduces a new trick where each pass in the group
retains a pointer to the top-most pass that has been initialized. This
allows passes to implement one API in terms of another API and benefit
when some other pass above them in the stack has more precise results
for the second API.
The second step of this conversion is to create a pass that implements
the TargetTransformInfo analysis using the target-independent
abstractions in the code generator. This replaces the
ScalarTargetTransformImpl and VectorTargetTransformImpl classes in
lib/Target with a single pass in lib/CodeGen called
BasicTargetTransformInfo. This class actually provides most of the TTI
functionality, basing it upon the TargetLowering abstraction and other
information in the target independent code generator.
The third step of the conversion adds support to all TargetMachines to
register custom analysis passes. This allows building those passes with
access to TargetLowering or other target-specific classes, and it also
allows each target to customize the set of analysis passes desired in
the pass manager. The baseline LLVMTargetMachine implements this
interface to add the BasicTTI pass to the pass manager, and all of the
tools that want to support target-aware TTI passes call this routine on
whatever target machine they end up with to add the appropriate passes.
The fourth step of the conversion created target-specific TTI analysis
passes for the X86 and ARM backends. These passes contain the custom
logic that was previously in their extensions of the
ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces.
I separated them into their own file, as now all of the interface bits
are private and they just expose a function to create the pass itself.
Then I extended these target machines to set up a custom set of analysis
passes, first adding BasicTTI as a fallback, and then adding their
customized TTI implementations.
The fourth step required logic that was shared between the target
independent layer and the specific targets to move to a different
interface, as they no longer derive from each other. As a consequence,
a helper functions were added to TargetLowering representing the common
logic needed both in the target implementation and the codegen
implementation of the TTI pass. While technically this is the only
change that could have been committed separately, it would have been
a nightmare to extract.
The final step of the conversion was just to delete all the old
boilerplate. This got rid of the ScalarTargetTransformInfo and
VectorTargetTransformInfo classes, all of the support in all of the
targets for producing instances of them, and all of the support in the
tools for manually constructing a pass based around them.
Now that TTI is a relatively normal analysis group, two things become
straightforward. First, we can sink it into lib/Analysis which is a more
natural layer for it to live. Second, clients of this interface can
depend on it *always* being available which will simplify their code and
behavior. These (and other) simplifications will follow in subsequent
commits, this one is clearly big enough.
Finally, I'm very aware that much of the comments and documentation
needs to be updated. As soon as I had this working, and plausibly well
commented, I wanted to get it committed and in front of the build bots.
I'll be doing a few passes over documentation later if it sticks.
Commits to update DragonEgg and Clang will be made presently.
llvm-svn: 171681
2013-01-07 09:37:14 +08:00
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InstrItins(&Subtarget.getInstrItineraryData()) {
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2013-05-13 09:16:13 +08:00
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initAsmInfo();
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2011-12-13 05:14:40 +08:00
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}
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2012-02-03 13:12:41 +08:00
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namespace {
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/// Hexagon Code Generator Pass Configuration Options.
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class HexagonPassConfig : public TargetPassConfig {
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public:
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2012-02-04 10:56:59 +08:00
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HexagonPassConfig(HexagonTargetMachine *TM, PassManagerBase &PM)
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2012-09-04 22:49:56 +08:00
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: TargetPassConfig(TM, PM) {
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2013-09-20 13:14:41 +08:00
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// FIXME: Rather than calling enablePass(&MachineSchedulerID) below, define
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// HexagonSubtarget::enableMachineScheduler() { return true; }.
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// That will bypass the SelectionDAG VLIW scheduler, which is probably just
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// hurting compile time and will be removed eventually anyway.
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if (DisableHexagonMISched)
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disablePass(&MachineSchedulerID);
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else
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2012-09-04 22:49:56 +08:00
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enablePass(&MachineSchedulerID);
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}
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2012-02-03 13:12:41 +08:00
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HexagonTargetMachine &getHexagonTargetMachine() const {
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return getTM<HexagonTargetMachine>();
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}
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2014-04-29 15:58:16 +08:00
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ScheduleDAGInstrs *
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createMachineScheduler(MachineSchedContext *C) const override {
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2013-09-20 13:14:41 +08:00
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return createVLIWMachineSched(C);
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}
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2014-04-29 15:58:16 +08:00
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bool addInstSelector() override;
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bool addPreRegAlloc() override;
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bool addPostRegAlloc() override;
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bool addPreSched2() override;
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bool addPreEmitPass() override;
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2012-02-03 13:12:41 +08:00
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};
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} // namespace
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2012-02-04 10:56:59 +08:00
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TargetPassConfig *HexagonTargetMachine::createPassConfig(PassManagerBase &PM) {
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return new HexagonPassConfig(this, PM);
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2012-02-03 13:12:41 +08:00
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}
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bool HexagonPassConfig::addInstSelector() {
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2013-06-20 05:36:55 +08:00
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HexagonTargetMachine &TM = getHexagonTargetMachine();
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2013-05-07 05:25:45 +08:00
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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2013-03-27 19:14:24 +08:00
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2013-05-07 05:25:45 +08:00
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if (!NoOpt)
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addPass(createHexagonRemoveExtendArgs(TM));
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2013-03-27 19:14:24 +08:00
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2013-05-07 05:25:45 +08:00
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addPass(createHexagonISelDag(TM, getOptLevel()));
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2013-03-27 19:14:24 +08:00
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2013-05-07 05:25:45 +08:00
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if (!NoOpt) {
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2013-03-27 19:14:24 +08:00
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addPass(createHexagonPeephole());
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2013-05-07 05:25:45 +08:00
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printAndVerify("After hexagon peephole pass");
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}
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2013-03-27 19:14:24 +08:00
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2011-12-13 05:14:40 +08:00
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return false;
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}
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2012-02-03 13:12:41 +08:00
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bool HexagonPassConfig::addPreRegAlloc() {
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2013-05-07 05:25:45 +08:00
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHardwareLoops)
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addPass(createHexagonHardwareLoops());
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2011-12-13 05:14:40 +08:00
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return false;
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}
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2012-02-03 13:12:41 +08:00
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bool HexagonPassConfig::addPostRegAlloc() {
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2013-05-07 05:25:45 +08:00
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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if (getOptLevel() != CodeGenOpt::None)
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if (!DisableHexagonCFGOpt)
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addPass(createHexagonCFGOptimizer(TM));
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return false;
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2011-12-13 05:14:40 +08:00
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}
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2012-02-03 13:12:41 +08:00
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bool HexagonPassConfig::addPreSched2() {
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2013-05-08 03:53:00 +08:00
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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2013-05-15 02:54:06 +08:00
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addPass(createHexagonCopyToCombine());
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2013-05-08 03:53:00 +08:00
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if (getOptLevel() != CodeGenOpt::None)
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addPass(&IfConverterID);
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2014-05-22 06:42:07 +08:00
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addPass(createHexagonSplitConst32AndConst64(TM));
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printAndVerify("After hexagon split const32/64 pass");
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2013-05-08 03:53:00 +08:00
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return true;
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2011-12-13 05:14:40 +08:00
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}
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2012-02-03 13:12:41 +08:00
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bool HexagonPassConfig::addPreEmitPass() {
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2013-05-07 05:25:45 +08:00
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const HexagonTargetMachine &TM = getHexagonTargetMachine();
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bool NoOpt = (getOptLevel() == CodeGenOpt::None);
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2011-12-13 05:14:40 +08:00
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2013-05-07 05:25:45 +08:00
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if (!NoOpt)
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2013-03-27 19:14:24 +08:00
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addPass(createHexagonNewValueJump());
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2012-05-12 13:10:30 +08:00
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2011-12-13 05:14:40 +08:00
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// Expand Spill code for predicate registers.
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2013-05-07 05:25:45 +08:00
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addPass(createHexagonExpandPredSpillCode(TM));
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2011-12-13 05:14:40 +08:00
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// Split up TFRcondsets into conditional transfers.
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2013-05-07 05:25:45 +08:00
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addPass(createHexagonSplitTFRCondSets(TM));
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2011-12-13 05:14:40 +08:00
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2012-05-04 05:52:53 +08:00
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// Create Packets.
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2013-05-07 05:25:45 +08:00
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if (!NoOpt) {
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if (!DisableHardwareLoops)
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addPass(createHexagonFixupHwLoops());
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2013-03-27 19:14:24 +08:00
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addPass(createHexagonPacketizer());
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2013-05-07 05:25:45 +08:00
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}
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2012-05-04 05:52:53 +08:00
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2011-12-13 05:14:40 +08:00
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return false;
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}
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