2013-05-07 00:15:19 +08:00
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//===-- SystemZAsmPrinter.cpp - SystemZ LLVM assembly printer -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Streams SystemZ assembly language and associated data, in the form of
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// MCInsts and MCExprs respectively.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZAsmPrinter.h"
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#include "InstPrinter/SystemZInstPrinter.h"
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#include "SystemZConstantPoolValue.h"
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#include "SystemZMCInstLower.h"
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#include "llvm/CodeGen/MachineModuleInfoImpls.h"
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#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
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2014-01-08 05:19:40 +08:00
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#include "llvm/IR/Mangler.h"
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2013-05-07 00:15:19 +08:00
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#include "llvm/MC/MCExpr.h"
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2013-09-25 18:20:08 +08:00
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#include "llvm/MC/MCInstBuilder.h"
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2013-05-07 00:15:19 +08:00
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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2013-09-25 19:11:53 +08:00
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GR32s.
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static MCInst lowerRILow(const MachineInstr *MI, unsigned Opcode) {
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2013-11-23 01:28:28 +08:00
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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2013-09-25 19:11:53 +08:00
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}
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2013-10-01 21:18:56 +08:00
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// Return an RI instruction like MI with opcode Opcode, but with the
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// GR64 register operands turned into GRH32s.
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static MCInst lowerRIHigh(const MachineInstr *MI, unsigned Opcode) {
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2013-11-23 01:28:28 +08:00
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if (MI->isCompare())
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(1).getImm());
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else
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
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.addImm(MI->getOperand(2).getImm());
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2013-10-01 21:18:56 +08:00
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}
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2013-10-01 19:26:28 +08:00
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// Return an RI instruction like MI with opcode Opcode, but with the
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// R2 register turned into a GR64.
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static MCInst lowerRIEfLow(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(MI->getOperand(0).getReg())
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.addReg(MI->getOperand(1).getReg())
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
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.addImm(MI->getOperand(3).getImm())
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.addImm(MI->getOperand(4).getImm())
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.addImm(MI->getOperand(5).getImm());
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}
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2015-02-18 17:13:27 +08:00
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static const MCSymbolRefExpr *getTLSGetOffset(MCContext &Context) {
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StringRef Name = "__tls_get_offset";
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2015-05-30 09:25:56 +08:00
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return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
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2015-02-18 17:13:27 +08:00
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MCSymbolRefExpr::VK_PLT,
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Context);
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}
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static const MCSymbolRefExpr *getGlobalOffsetTable(MCContext &Context) {
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StringRef Name = "_GLOBAL_OFFSET_TABLE_";
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2015-05-30 09:25:56 +08:00
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return MCSymbolRefExpr::create(Context.getOrCreateSymbol(Name),
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2015-02-18 17:13:27 +08:00
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MCSymbolRefExpr::VK_None,
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Context);
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}
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2015-05-06 03:28:34 +08:00
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// MI loads the high part of a vector from memory. Return an instruction
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// that uses replicating vector load Opcode to do the same thing.
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static MCInst lowerSubvectorLoad(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(MI->getOperand(3).getReg());
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}
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// MI stores the high part of a vector to memory. Return an instruction
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// that uses elemental vector store Opcode to do the same thing.
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static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
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return MCInstBuilder(Opcode)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addImm(MI->getOperand(2).getImm())
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.addReg(MI->getOperand(3).getReg())
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.addImm(0);
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}
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2013-05-07 00:15:19 +08:00
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void SystemZAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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2013-10-30 00:18:15 +08:00
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SystemZMCInstLower Lower(MF->getContext(), *this);
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2013-05-07 00:15:19 +08:00
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MCInst LoweredMI;
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2013-09-25 18:20:08 +08:00
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switch (MI->getOpcode()) {
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case SystemZ::Return:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D);
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break;
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2013-09-25 18:37:17 +08:00
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case SystemZ::CallBRASL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBASR:
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LoweredMI = MCInstBuilder(SystemZ::BASR)
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.addReg(SystemZ::R14D)
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.addReg(MI->getOperand(0).getReg());
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break;
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case SystemZ::CallJG:
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LoweredMI = MCInstBuilder(SystemZ::JG)
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_PLT));
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break;
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case SystemZ::CallBR:
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LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D);
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break;
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2015-02-18 17:13:27 +08:00
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case SystemZ::TLS_GDCALL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(getTLSGetOffset(MF->getContext()))
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSGD));
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break;
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case SystemZ::TLS_LDCALL:
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LoweredMI = MCInstBuilder(SystemZ::BRASL)
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.addReg(SystemZ::R14D)
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.addExpr(getTLSGetOffset(MF->getContext()))
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.addExpr(Lower.getExpr(MI->getOperand(0), MCSymbolRefExpr::VK_TLSLDM));
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break;
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case SystemZ::GOT:
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LoweredMI = MCInstBuilder(SystemZ::LARL)
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.addReg(MI->getOperand(0).getReg())
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.addExpr(getGlobalOffsetTable(MF->getContext()));
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break;
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2013-09-25 19:11:53 +08:00
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case SystemZ::IILF64:
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LoweredMI = MCInstBuilder(SystemZ::IILF)
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.addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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2013-10-01 21:02:28 +08:00
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case SystemZ::IIHF64:
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LoweredMI = MCInstBuilder(SystemZ::IIHF)
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.addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
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.addImm(MI->getOperand(2).getImm());
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break;
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2013-10-01 19:26:28 +08:00
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case SystemZ::RISBHH:
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case SystemZ::RISBHL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBHG);
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break;
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case SystemZ::RISBLH:
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case SystemZ::RISBLL:
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LoweredMI = lowerRIEfLow(MI, SystemZ::RISBLG);
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break;
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[SystemZ] Add CodeGen support for integer vector types
This the first of a series of patches to add CodeGen support exploiting
the instructions of the z13 vector facility. This patch adds support
for the native integer vector types (v16i8, v8i16, v4i32, v2i64).
When the vector facility is present, we default to the new vector ABI.
This is characterized by two major differences:
- Vector types are passed/returned in vector registers
(except for unnamed arguments of a variable-argument list function).
- Vector types are at most 8-byte aligned.
The reason for the choice of 8-byte vector alignment is that the hardware
is able to efficiently load vectors at 8-byte alignment, and the ABI only
guarantees 8-byte alignment of the stack pointer, so requiring any higher
alignment for vectors would require dynamic stack re-alignment code.
However, for compatibility with old code that may use vector types, when
*not* using the vector facility, the old alignment rules (vector types
are naturally aligned) remain in use.
These alignment rules are not only implemented at the C language level
(implemented in clang), but also at the LLVM IR level. This is done
by selecting a different DataLayout string depending on whether the
vector ABI is in effect or not.
Based on a patch by Richard Sandiford.
llvm-svn: 236521
2015-05-06 03:25:42 +08:00
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case SystemZ::VLVGP32:
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LoweredMI = MCInstBuilder(SystemZ::VLVGP)
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.addReg(MI->getOperand(0).getReg())
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
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break;
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2015-05-06 03:28:34 +08:00
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case SystemZ::VLR32:
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case SystemZ::VLR64:
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LoweredMI = MCInstBuilder(SystemZ::VLR)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
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break;
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case SystemZ::VL32:
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LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPF);
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break;
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case SystemZ::VL64:
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LoweredMI = lowerSubvectorLoad(MI, SystemZ::VLREPG);
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break;
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case SystemZ::VST32:
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LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEF);
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break;
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case SystemZ::VST64:
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LoweredMI = lowerSubvectorStore(MI, SystemZ::VSTEG);
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break;
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2015-05-06 03:27:45 +08:00
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case SystemZ::LFER:
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LoweredMI = MCInstBuilder(SystemZ::VLGVF)
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.addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
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.addReg(0).addImm(0);
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break;
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case SystemZ::LEFR:
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LoweredMI = MCInstBuilder(SystemZ::VLVGF)
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
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.addReg(MI->getOperand(1).getReg())
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.addReg(0).addImm(0);
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break;
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2013-09-25 19:11:53 +08:00
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#define LOWER_LOW(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRILow(MI, SystemZ::NAME); break
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LOWER_LOW(IILL);
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LOWER_LOW(IILH);
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2013-11-23 01:28:28 +08:00
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LOWER_LOW(TMLL);
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LOWER_LOW(TMLH);
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2013-09-25 19:11:53 +08:00
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LOWER_LOW(NILL);
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LOWER_LOW(NILH);
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LOWER_LOW(NILF);
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LOWER_LOW(OILL);
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LOWER_LOW(OILH);
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LOWER_LOW(OILF);
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LOWER_LOW(XILF);
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#undef LOWER_LOW
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2013-10-01 21:18:56 +08:00
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#define LOWER_HIGH(NAME) \
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case SystemZ::NAME##64: LoweredMI = lowerRIHigh(MI, SystemZ::NAME); break
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LOWER_HIGH(IIHL);
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LOWER_HIGH(IIHH);
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2013-11-23 01:28:28 +08:00
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LOWER_HIGH(TMHL);
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LOWER_HIGH(TMHH);
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2013-10-01 22:20:41 +08:00
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LOWER_HIGH(NIHL);
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LOWER_HIGH(NIHH);
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LOWER_HIGH(NIHF);
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2013-10-01 21:22:41 +08:00
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LOWER_HIGH(OIHL);
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LOWER_HIGH(OIHH);
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LOWER_HIGH(OIHF);
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2013-10-01 22:08:44 +08:00
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LOWER_HIGH(XIHF);
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2013-10-01 21:18:56 +08:00
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#undef LOWER_HIGH
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2013-12-10 18:36:34 +08:00
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case SystemZ::Serialize:
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2015-02-19 09:26:28 +08:00
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if (MF->getSubtarget<SystemZSubtarget>().hasFastSerialization())
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2013-12-10 18:36:34 +08:00
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LoweredMI = MCInstBuilder(SystemZ::AsmBCR)
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.addImm(14).addReg(SystemZ::R0D);
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else
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LoweredMI = MCInstBuilder(SystemZ::AsmBCR)
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.addImm(15).addReg(SystemZ::R0D);
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break;
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2013-09-25 18:20:08 +08:00
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default:
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2013-09-25 18:37:17 +08:00
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Lower.lower(MI, LoweredMI);
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2013-09-25 18:20:08 +08:00
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break;
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}
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2015-04-25 03:11:51 +08:00
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EmitToStreamer(*OutStreamer, LoweredMI);
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2013-05-07 00:15:19 +08:00
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}
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// Convert a SystemZ-specific constant pool modifier into the associated
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// MCSymbolRefExpr variant kind.
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static MCSymbolRefExpr::VariantKind
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getModifierVariantKind(SystemZCP::SystemZCPModifier Modifier) {
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switch (Modifier) {
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2015-02-18 17:13:27 +08:00
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case SystemZCP::TLSGD: return MCSymbolRefExpr::VK_TLSGD;
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case SystemZCP::TLSLDM: return MCSymbolRefExpr::VK_TLSLDM;
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case SystemZCP::DTPOFF: return MCSymbolRefExpr::VK_DTPOFF;
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2013-05-07 00:15:19 +08:00
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case SystemZCP::NTPOFF: return MCSymbolRefExpr::VK_NTPOFF;
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}
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llvm_unreachable("Invalid SystemCPModifier!");
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}
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void SystemZAsmPrinter::
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EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
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2014-03-06 19:22:58 +08:00
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auto *ZCPV = static_cast<SystemZConstantPoolValue*>(MCPV);
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2013-05-07 00:15:19 +08:00
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const MCExpr *Expr =
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2015-05-30 09:25:56 +08:00
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MCSymbolRefExpr::create(getSymbol(ZCPV->getGlobalValue()),
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2013-05-07 00:15:19 +08:00
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getModifierVariantKind(ZCPV->getModifier()),
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OutContext);
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2015-01-27 03:03:15 +08:00
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uint64_t Size = TM.getDataLayout()->getTypeAllocSize(ZCPV->getType());
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2013-05-07 00:15:19 +08:00
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2015-04-25 03:11:51 +08:00
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OutStreamer->EmitValue(Expr, Size);
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2013-05-07 00:15:19 +08:00
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}
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bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI,
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|
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unsigned OpNo,
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unsigned AsmVariant,
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|
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const char *ExtraCode,
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|
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|
raw_ostream &OS) {
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|
|
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if (ExtraCode && *ExtraCode == 'n') {
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if (!MI->getOperand(OpNo).isImm())
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|
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return true;
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|
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OS << -int64_t(MI->getOperand(OpNo).getImm());
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|
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} else {
|
2013-10-30 00:18:15 +08:00
|
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SystemZMCInstLower Lower(MF->getContext(), *this);
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2013-05-07 00:15:19 +08:00
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MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
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SystemZInstPrinter::printOperand(MO, OS);
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}
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return false;
|
|
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}
|
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|
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bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
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|
|
|
unsigned OpNo,
|
|
|
|
unsigned AsmVariant,
|
|
|
|
const char *ExtraCode,
|
|
|
|
raw_ostream &OS) {
|
|
|
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SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
|
|
|
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MI->getOperand(OpNo + 1).getImm(),
|
|
|
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MI->getOperand(OpNo + 2).getReg(), OS);
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|
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return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Force static initialization.
|
|
|
|
extern "C" void LLVMInitializeSystemZAsmPrinter() {
|
|
|
|
RegisterAsmPrinter<SystemZAsmPrinter> X(TheSystemZTarget);
|
|
|
|
}
|