The first phase of Open Verification for the Kunminghu microarchitecture of Xiangshan: Kunminghu's BPU Module UT Verification in Action.

中文文档

This project aims to explore open-sourced subdivision verification of the high-performance open-source RISC-V OpenXiangshan processor's microarchitecture. It introduces new tools and methods based on Python, enabling all students interested in chip design and verification to quickly grasp and study the XiangShan microarchitecture. This phase provides a detailed introduction to the principles and implementation of the branch prediction module of the XiangShan Kunminghu architecture, along with the corresponding open-source verification environment. Participants in this phase can earn points and rewards by submitting bugs, writing verification reports, and more.

The Open Verification Porject website：open-verify.cc

Introduction

This project utilizes open-source tools for the open verification of open-source chips. The focus of the current phase is the BPU module within the XiangShan Kunminghu microarchitecture.

Kunminghu microarchitecture

The Kunminghu architecture is the third-generation high-performance microarchitecture of the XiangShan open-source processor. For the architecture diagram, please refer to the Kunminghu architecture diagram.

Chip verification

Chip validation is a crucial aspect of chip design work. Skipping or insufficient validation can result in chip fabrication failures or products not meeting standards, leading to significant losses. Chip design companies treat chip design as proprietary business secrets, and chip validation typically requires access to the chip design source code. Therefore, chip validation work can only be conducted internally within the company. However, with the open-source nature of the Shanhai high-performance RISC-V chip, concerns about "leaking proprietary secrets" do not arise. Consequently, chip validation work can be distributed in a manner similar to software subcontracting or crowdsourcing, allowing interested individuals to participate remotely.

Learning resources

1. Basic Learning Materials: Learn about chip validation and how to use Python for validation.

2. Introduction to Shanhai BPU: Learn about branch prediction and the basic predictors used in the Shanhai processor.

3. How to Participate in This Activity: Learn how to participate in this activity and the rules.

4. Building Verification Environment: Learn how to set up the basic verification environment, how to validate, and submit validation results.

To accelerate the verification process, the verification environment has provided the following reusable features:

• Python DUT: Python module corresponding to each module to be verified
• FakeFTQ: A general interface for driving BPU, providing operations such as redirect and update
• BPU Trace: Branch jump data of real applications
• Pytest environment: Drive tests through pytest, generate test reports, provide code line coverage, and function coverage support

For details, please refer to the test Demo: uFTB-raw, uFTB-with-ftq

Repository Directory

The structure of this repository directory and corresponding explanations are as follows:

.
├── doc
├── image
├── LICENSE
├── Makefile
├── mk               # Sub Makefiles
├── Readme_cn.md
├── Readme.md
├── tests            # Tests dir    <- put your test code here !
│   ├── Makefile        # Test Makefile
│   ├── conftest.py     # Pytest config
│   ├── README.md       # Test readme
│   ├── uFTB_raw        # Example 1
│   └── uftb-with-ftq   # Example 2
└── utils            # Tools you may need
    ├── BRTParser       # Branc trace parser
    └── ready-to-run    # Binary files to run (trace source)

Note: Since this project requires submitting results via PR, please make sure to organize the data according to the directory requirements mentioned above.

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