forked from XS-MLVP/env-xs-ov-00-bpu
finish ittage top init version
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b511a0dd00
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c641d911f3
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@ -155,6 +155,8 @@ class ITTAGEInfo(ITTAGEInterReg, ITTAGELastStageMeta):
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self.jmp_taken = 0
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self.cfi_idx_valid = 0
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self.cfi_idx = 0
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# only used for dut
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self.meta_str = ""
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def clear(self) -> None:
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self.is_trace = 0
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@ -167,6 +169,7 @@ class ITTAGEInfo(ITTAGEInterReg, ITTAGELastStageMeta):
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self.ftb_entry_tailslot_valid = 0
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self.ftb_entry_is_jalr = 0
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self.ftb_entry_is_ret = 0
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self.meta_str = ""
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self.reinit()
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def log(self, stage: int = 0) -> None:
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@ -337,7 +340,7 @@ class ITTAGEModel:
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def update(self, update: ITTAGEInfo) -> None:
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_update_valid = update.update_valid and update.ftb_entry_is_jalr and not update.ftb_entry_is_ret and \
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update.ftb_entry_tailslot_valid and not update.ftb_entry_tailslot_sharing and \
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update.jmp_taken and update.cfi_idx_valid and update.cif_idx == update.ftb_entry_tailslot_offset
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update.jmp_taken and update.cfi_idx_valid and update.cfi_idx == update.ftb_entry_tailslot_offset
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# Every cycle only enable one update transaction
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if _update_valid and not self.update_q.empty() and self.update_q.queue[0][1] != self.cycles:
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self.update_q.put((update, self.cycles + 2))
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@ -14,7 +14,7 @@ import queue
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import random
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class ITTAGETop:
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def __init__(self, dut: DUTITTage, log_mode: int = 0) -> None:
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def __init__(self, dut: DUTITTage = None, log_mode: int = 0) -> None:
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self.dut = dut
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self.ref = ITTAGEModel(log_mode)
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# input in current cycle
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@ -31,14 +31,31 @@ class ITTAGETop:
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self.latency = 20
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# for debug
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self.log_mode = log_mode
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self.has_dut = isinstance(dut, DUTITTage)
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def _gen_ref_output(self) -> ITTAGEInfo:
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# Get ref output
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return self.ref.get_output()
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def _gen_dut_output(self) -> ITTAGEInfo:
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# TODO: Get DUT output
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raise NotImplementedError
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if not self.has_dut:
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return ITTAGEInfo()
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_dut_out = ITTAGEInfo()
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_dut_out.meta_str = self.dut.io_out_last_stage_meta.xdata.AsBinaryString()
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_meta_str = self.dut.io_out_last_stage_meta.xdata.AsBinaryString()[::-1].ljust(101, '0')
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_dut_out.has_provider = int(_meta_str[100] == '1')
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_dut_out.provider = int(_meta_str[97:100][::-1], 2)
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_dut_out.has_alt = int(_meta_str[96] == '1')
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_dut_out.alt = int(_meta_str[93:96][::-1], 2)
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_dut_out.alt_differs = int(_meta_str[92] == '1')
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_dut_out.provider_u = int(_meta_str[91] == '1')
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_dut_out.provider_ctr = int(_meta_str[89:91][::-1], 2)
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_dut_out.alt_ctr = int(_meta_str[87:89][::-1], 2)
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_dut_out.alloc_valid = int(_meta_str[86] == '1')
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_dut_out.alloc_table = int(_meta_str[83:86][::-1], 2)
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_dut_out.provider_target = int(_meta_str[41:82][::-1], 2)
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_dut_out.alt_target = int(_meta_str[0:41][::-1], 2)
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return _dut_out
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def _assign_update_sig(self, update: ITTAGEInfo):
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update.update_valid = 1
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@ -49,13 +66,14 @@ class ITTAGETop:
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update.ftb_entry_is_jalr = 1
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update.ftb_entry_is_ret = 0
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update.jmp_taken = 1
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update.cfi_idx_valid = 0
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update.cfi_idx_valid = 1
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update.cfi_idx = index
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return self
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def _assign_dut_alloc_to_ref(self, ref_info: ITTAGEInfo, dut_info: ITTAGEInfo):
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def _assign_dut_meta_to_ref(self, ref_info: ITTAGEInfo, dut_info: ITTAGEInfo):
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ref_info.alloc_valid = dut_info.alloc_valid
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ref_info.alloc_table = dut_info.alloc_table
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ref_info.meta_str = dut_info.meta_str
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def _assign_mispred(self, out_info: ITTAGEInfo):
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# When no provider, set mispred to allocate new table item
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@ -72,6 +90,8 @@ class ITTAGETop:
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return self
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def _compare_dut_ref_output(self, ref_info: ITTAGEInfo, dut_info: ITTAGEInfo) -> bool:
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if not self.has_dut:
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return True
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if not ref_info.check_provider(dut_info.has_provider, dut_info.provider, \
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dut_info.provider_u, dut_info.provider_ctr, dut_info.provider_target):
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return False
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@ -97,6 +117,8 @@ class ITTAGETop:
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self.ref.cycle(_input_info)
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def _dut_input_and_step(self):
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if not self.has_dut:
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return
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# Set DUT pipeline shake hand signal
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self.dut.io_s0_fire_3.xdata.value = self.s0_fire
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self.dut.io_s1_fire_3.xdata.value = self.s1_fire
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@ -114,7 +136,35 @@ class ITTAGETop:
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self.dut.Step(1)
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def _assign_dut_update(self, update: ITTAGEInfo = None):
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raise NotImplementedError
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# TODO: assign DUT update signals
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# no DUT or no update valid in this cycle
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if not self.has_dut:
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return
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if not isinstance(update, ITTAGEInfo):
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self.dut.io_update_valid = 0
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return
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# assign update signals in DUT
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self.dut.io_update_valid.xdata.value = 1
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self.dut.io_update_bits_pc.xdata.value = update.pc
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self.dut.io_update_bits_spec_info_folded_hist_hist_12_folded_hist.xdata.value = update.folded_hists[0]
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self.dut.io_update_bits_spec_info_folded_hist_hist_14_folded_hist.xdata.value = update.folded_hists[1]
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self.dut.io_update_bits_spec_info_folded_hist_hist_13_folded_hist.xdata.value = update.folded_hists[2][0]
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self.dut.io_update_bits_spec_info_folded_hist_hist_4_folded_hist.xdata.value = update.folded_hists[2][1]
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self.dut.io_update_bits_spec_info_folded_hist_hist_6_folded_hist.xdata.value = update.folded_hists[3][0]
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self.dut.io_update_bits_spec_info_folded_hist_hist_2_folded_hist.xdata.value = update.folded_hists[3][1]
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self.dut.io_update_bits_spec_info_folded_hist_hist_10_folded_hist.xdata.value = update.folded_hists[4][0]
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self.dut.io_update_bits_spec_info_folded_hist_hist_3_folded_hist.xdata.value = update.folded_hists[4][1]
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self.dut.io_update_bits_ftb_entry_isJalr.xdata.value = update.ftb_entry_is_jalr
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self.dut.io_update_bits_ftb_entry_isRet.xdata.value = update.ftb_entry_is_ret
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self.dut.io_update_bits_ftb_entry_tailSlot_valid.xdata.value = update.ftb_entry_tailslot_valid
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self.dut.io_update_bits_ftb_entry_tailSlot_sharing.xdata.value = update.ftb_entry_tailslot_sharing
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self.dut.io_update_bits_ftb_entry_tailSlot_offset.xdata.value = update.ftb_entry_tailslot_offset
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self.dut.io_update_bits_cfi_idx_valid.xdata.value = update.cfi_idx_valid
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self.dut.io_update_bits_cfi_idx_bits.xdata.value = update.cfi_idx
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self.dut.io_update_bits_jmp_taken.xdata.value = update.jmp_taken
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self.dut.io_update_bits_mispred_mask_2.xdata.value = update.mispred
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self.dut.io_update_bits_meta.xdata.value = '0b' + update.meta_str
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self.dut.io_update_bits_full_target.xdata.value = update.target
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def _log_info(self, ref_info: ITTAGEInfo, dut_info: ITTAGEInfo):
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# basic meta log
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@ -141,7 +191,7 @@ class ITTAGETop:
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# ------------- Gen DUT Output --------------
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_out_dut_info = self._gen_dut_output()
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# ------------- Outpur Comparision --------------
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# ------------- Output Comparision --------------
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if self.log_mode == 1:
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self._log_info(_out_ref_info, _out_dut_info)
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if self._compare_dut_ref_output(_out_ref_info, _out_dut_info):
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@ -151,7 +201,7 @@ class ITTAGETop:
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# Generate update feedback to ITTAGE (Only for traced signal)
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if _out_ref_info.is_trace:
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self._assign_update_sig(_out_ref_info)
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self._assign_dut_alloc_to_ref(_out_ref_info, _out_dut_info)
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self._assign_dut_meta_to_ref(_out_ref_info, _out_dut_info)
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self._assign_mispred(_out_ref_info)
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# push update info to queue and set random latency for each update
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self.update_q.put((_out_ref_info, self.cycles + self.latency))
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