forked from XS-MLVP/env-xs-ov-00-bpu
Change the FTQ bundle to new bundle
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@ -136,7 +136,7 @@ class BPUTop:
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# Get dut output and generate bpu output
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dut_output = self.dut_out.collect()
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dut_output = self.dut_out.as_dict()
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bpu_output = self.generate_bpu_output(dut_output)
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ftb_entry = FTBEntry.from_full_pred_dict(self.s1_pc, dut_output["s1"]["full_pred"])
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@ -1,51 +1,53 @@
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from mlvp import Bundle
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class PipelineCtrlBundle(Bundle):
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signals_list = ["s0_fire_0", "s0_fire_1", "s0_fire_2", "s0_fire_3",
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"s1_fire_0", "s1_fire_1", "s1_fire_2", "s1_fire_3",
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"s2_fire_0", "s2_fire_1", "s2_fire_2", "s2_fire_3",
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"s3_fire_0", "s3_fire_1", "s3_fire_2", "s3_fire_3",
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"s1_ready", "s2_ready", "s3_ready",
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"s2_redirect", "s3_redirect"]
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signals = ["s0_fire_0", "s0_fire_1", "s0_fire_2", "s0_fire_3",
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"s1_fire_0", "s1_fire_1", "s1_fire_2", "s1_fire_3",
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"s2_fire_0", "s2_fire_1", "s2_fire_2", "s2_fire_3",
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"s3_fire_0", "s3_fire_1", "s3_fire_2", "s3_fire_3",
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"s1_ready", "s2_ready", "s3_ready",
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"s2_redirect", "s3_redirect"]
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class EnableCtrlBundle(Bundle):
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signals_list = ["ubtb_enable", "btb_enable", "bim_enable", "tage_enable",
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"sc_enable", "ras_enable", "loop_enable"]
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signals = ["ubtb_enable", "btb_enable", "bim_enable", "tage_enable",
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"sc_enable", "ras_enable", "loop_enable"]
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class FTBEntryBundle(Bundle):
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signals_list = ["brSlots_0_offset", "brSlots_0_lower", "brSlots_0_tarStat", "brSlots_0_valid",
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"tailSlot_offset", "tailSlot_lower", "tailSlot_tarStat", "tailSlot_sharing", "tailSlot_valid",
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"pftAddr", "carry", "isCall", "isRet", "isJalr", "last_may_be_rvi_call",
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"always_taken_0", "always_taken_1"]
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signals = ["brSlots_0_offset", "brSlots_0_lower", "brSlots_0_tarStat", "brSlots_0_valid",
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"tailSlot_offset", "tailSlot_lower", "tailSlot_tarStat", "tailSlot_sharing", "tailSlot_valid",
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"pftAddr", "carry", "isCall", "isRet", "isJalr", "last_may_be_rvi_call",
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"always_taken_0", "always_taken_1"]
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class UpdateBundle(Bundle):
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signals_list = ["valid", "bits_pc", "bits_br_taken_mask_0", "bits_br_taken_mask_1"]
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signals = ["valid", "bits_pc", "bits_br_taken_mask_0", "bits_br_taken_mask_1"]
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sub_bundles = [
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("ftb_entry", lambda dut: FTBEntryBundle.from_prefix(dut, "bits_ftb_entry_"))
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]
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def __init__(self):
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super().__init__()
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self.ftb_entry = FTBEntryBundle.from_prefix("bits_ftb_entry_")
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class FullBranchPredirectionBundle(Bundle):
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signals_list = ["hit", "slot_valids_0", "slot_valids_1", "targets_0", "targets_1",
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"offsets_0", "offsets_1", "fallThroughAddr", "fallThroughErr",
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"is_jal", "is_jalr", "is_call", "is_ret", "is_br_sharing",
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"last_may_be_rvi_call",
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"br_taken_mask_0", "br_taken_mask_1",
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"jalr_target"]
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signals = ["hit", "slot_valids_0", "slot_valids_1", "targets_0", "targets_1",
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"offsets_0", "offsets_1", "fallThroughAddr", "fallThroughErr",
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"is_jal", "is_jalr", "is_call", "is_ret", "is_br_sharing",
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"last_may_be_rvi_call",
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"br_taken_mask_0", "br_taken_mask_1",
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"jalr_target"]
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class BranchPredictionBundle(Bundle):
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signals_list = ["pc_3", "valid", "hasRedirect", "ftq_idx"]
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sub_bundles = [
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("full_pred", lambda dut: FullBranchPredirectionBundle.from_regex(dut, r"full_pred_\d_(.*)"))
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]
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signals = ["pc_3", "valid", "hasRedirect", "ftq_idx"]
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def __init__(self):
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super().__init__()
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self.full_pred = FullBranchPredirectionBundle.from_regex(r"full_pred_\d_(.*)")
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class BranchPredictionResp(Bundle):
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signals_list = ["last_stage_meta"]
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sub_bundles = [
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("s1", lambda dut: BranchPredictionBundle.from_prefix(dut, "s1_")),
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("s2", lambda dut: BranchPredictionBundle.from_prefix(dut, "s2_")),
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("s3", lambda dut: BranchPredictionBundle.from_prefix(dut, "s3_")),
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("last_stage_ftb_entry", lambda dut: FTBEntryBundle.from_prefix(dut, "last_stage_ftb_entry_"))
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]
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signals = ["last_stage_meta"]
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def __init__(self):
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super().__init__()
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self.s1 = BranchPredictionBundle.from_prefix("s1_")
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self.s2 = BranchPredictionBundle.from_prefix("s2_")
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self.s3 = BranchPredictionBundle.from_prefix("s3_")
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self.last_stage_ftb_entry = FTBEntryBundle.from_prefix("last_stage_ftb_entry_")
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@ -24,10 +24,10 @@ def set_imm_mode(uFTB):
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async def uftb_test(uFTB):
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uFTB_update = UpdateBundle.from_prefix(uFTB, "io_update_")
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uFTB_out = BranchPredictionResp.from_prefix(uFTB, "io_out_")
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pipeline_ctrl = PipelineCtrlBundle.from_prefix(uFTB, "io_")
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enable_ctrl = EnableCtrlBundle.from_prefix(uFTB, "io_ctrl_")
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uFTB_update = UpdateBundle.from_prefix("io_update_").set_name("uFTB_update").bind(uFTB)
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uFTB_out = BranchPredictionResp.from_prefix("io_out_").set_name("uFTB_out").bind(uFTB)
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pipeline_ctrl = PipelineCtrlBundle.from_prefix("io_").set_name("pipeline_ctrl").bind(uFTB)
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enable_ctrl = EnableCtrlBundle.from_prefix("io_ctrl_").set_name("enable_ctrl").bind(uFTB)
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mlvp.create_task(mlvp.start_clock(uFTB))
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mlvp.create_task(BPUTop(uFTB, uFTB_out, uFTB_update, pipeline_ctrl, enable_ctrl).run())
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@ -74,3 +74,4 @@ def test_uftb(request):
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pred_stat.summary()
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set_func_coverage(request, [g1, g2])
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set_line_coverage(request, "report/uftb_with_ftq_coverage.dat")
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