finalize() to Finish() in new mlvp

tests/ITTAGE_alloc/test_alloc.py

@@ -97,7 +97,7 @@ def test_ittage_alloc():
     run_test_tick_ctr(ittage)
     print('========================== test ITTAGE tickCtr end ==========================')
 
-    ittage.finalize()
+    ittage.Finish()
 
 if __name__ == '__main__':
     test_ittage_alloc()

tests/ITTAGE_alt_provider/test_alt_provider.py

@@ -184,7 +184,7 @@ def test_ittage_alt_provider():
     run_alt_differs(ittage, '100', '011')
     print('========================== test ITTAGE alt differs end ==========================')
 
-    ittage.finalize()
+    ittage.Finish()
 
 
 if __name__ == "__main__":

tests/ITTAGE_ctr/test_ctr.py

@@ -151,7 +151,7 @@ def test_ittage_ctr():
     run_ctr_alt_provider(ittage, '100', '011')
     print('========================== test ITTAGE ctr with alt provider end ==========================')
 
-    ittage.finalize()
+    ittage.Finish()
 
 
 if __name__ == "__main__":

tests/ITTAGE_provider/test_provider.py

@@ -71,7 +71,7 @@ def test_ittage_provider():
     metas[5].check_provided('1').check_provider('100').check_providerCtr('10').check_providerTarget(target)
     print('========================== test end ==========================\n\n')
 
-    ittage.finalize()
+    ittage.Finish()
 
 
 

tests/ITTAGE_raw/test_raw.py

@@ -219,11 +219,11 @@ class LastStageMeta:
 
 
 def reset_init(ittage: DUTITTage):
-    ittage.init_clock("clock")
-    ittage.io_update_valid.value = 0
-    ittage.reset.value = 1
+    ittage.InitClock("clock")
+    ittage.io_update_valid.xdata.value = 0
+    ittage.reset.xdata.value = 1
     ittage.Step(100)
-    ittage.reset.value = 0
+    ittage.reset.xdata.value = 0
     ittage.Step(512)
     print("ITTAGE initialized")
 
@@ -234,23 +234,23 @@ def drive_full_pred(ittage: DUTITTage, pc: int, ftb_target: int, fh: FoldedHists
         print(f'pc={hex(pc)}')
         print(f'ftb_target={hex(ftb_target)}')
 
-    ittage.io_update_valid.value = 0
-    ittage.io_in_bits_s0_pc_3.value = pc
-    ittage.io_in_bits_folded_hist_3_hist_12_folded_hist.value = fh.get_t1_fh()
-    ittage.io_in_bits_folded_hist_3_hist_14_folded_hist.value = fh.get_t2_fh()
-    ittage.io_in_bits_folded_hist_3_hist_13_folded_hist.value, ittage.io_in_bits_folded_hist_3_hist_4_folded_hist.value = fh.get_t3_fh()
-    ittage.io_in_bits_folded_hist_3_hist_6_folded_hist.value, ittage.io_in_bits_folded_hist_3_hist_2_folded_hist.value = fh.get_t4_fh()
-    ittage.io_in_bits_folded_hist_3_hist_10_folded_hist.value, ittage.io_in_bits_folded_hist_3_hist_3_folded_hist.value = fh.get_t5_fh()
-    ittage.io_in_bits_resp_in_0_s2_full_pred_3_jalr_target.value = ftb_target
-    ittage.io_s0_fire_3.value = 1
+    ittage.io_update_valid.xdata.value = 0
+    ittage.io_in_bits_s0_pc_3.xdata.value = pc
+    ittage.io_in_bits_folded_hist_3_hist_12_folded_hist.xdata.value = fh.get_t1_fh()
+    ittage.io_in_bits_folded_hist_3_hist_14_folded_hist.xdata.value = fh.get_t2_fh()
+    ittage.io_in_bits_folded_hist_3_hist_13_folded_hist.xdata.value, ittage.io_in_bits_folded_hist_3_hist_4_folded_hist.xdata.value = fh.get_t3_fh()
+    ittage.io_in_bits_folded_hist_3_hist_6_folded_hist.xdata.value, ittage.io_in_bits_folded_hist_3_hist_2_folded_hist.xdata.value = fh.get_t4_fh()
+    ittage.io_in_bits_folded_hist_3_hist_10_folded_hist.xdata.value, ittage.io_in_bits_folded_hist_3_hist_3_folded_hist.xdata.value = fh.get_t5_fh()
+    ittage.io_in_bits_resp_in_0_s2_full_pred_3_jalr_target.xdata.value = ftb_target
+    ittage.io_s0_fire_3.xdata.value = 1
     ittage.Step(1)
-    ittage.io_s0_fire_3.value = 0
-    ittage.io_s1_fire_3.value = 1
+    ittage.io_s0_fire_3.xdata.value = 0
+    ittage.io_s1_fire_3.xdata.value = 1
     ittage.Step(1)
-    ittage.io_s1_fire_3.value = 0
-    ittage.io_s2_fire_3.value = 1
+    ittage.io_s1_fire_3.xdata.value = 0
+    ittage.io_s2_fire_3.xdata.value = 1
     ittage.Step(1)
-    ittage.io_s2_fire_3.value = 0
+    ittage.io_s2_fire_3.xdata.value = 0
     ittage.Step(2)
 
     s3_meta = LastStageMeta(ittage.io_out_last_stage_meta.xdata.AsBinaryString()[::-1])
@@ -272,26 +272,26 @@ def drive_full_update(ittage: DUTITTage, pc: int, fh: FoldedHists, target: int,
         print("--------------------- ITTAGE Full Update Drive ---------------------")
         print(f'pc={hex(pc)}\nfull_target={hex(target)}\ncfi_idx={cfi_idx}\nmispred={mispred}\n')
         meta.print()
-    ittage.io_update_valid.value = 1
-    ittage.io_update_bits_pc.value = pc
-    ittage.io_update_bits_spec_info_folded_hist_hist_12_folded_hist.value = fh.get_t1_fh()
-    ittage.io_update_bits_spec_info_folded_hist_hist_14_folded_hist.value = fh.get_t2_fh()
-    ittage.io_update_bits_spec_info_folded_hist_hist_13_folded_hist.value, ittage.io_update_bits_spec_info_folded_hist_hist_4_folded_hist.value = fh.get_t3_fh()
-    ittage.io_update_bits_spec_info_folded_hist_hist_6_folded_hist.value, ittage.io_update_bits_spec_info_folded_hist_hist_2_folded_hist.value = fh.get_t4_fh()
-    ittage.io_update_bits_spec_info_folded_hist_hist_10_folded_hist.value, ittage.io_update_bits_spec_info_folded_hist_hist_3_folded_hist.value = fh.get_t5_fh()
-    ittage.io_update_bits_ftb_entry_isJalr.value = 1
-    ittage.io_update_bits_ftb_entry_isRet.value = 0
-    ittage.io_update_bits_ftb_entry_tailSlot_valid.value = 1
-    ittage.io_update_bits_ftb_entry_tailSlot_sharing.value = 0 # non-conditional jump
-    ittage.io_update_bits_ftb_entry_tailSlot_offset.value = cfi_idx
-    ittage.io_update_bits_cfi_idx_valid.value = 1
-    ittage.io_update_bits_cfi_idx_bits.value = cfi_idx
-    ittage.io_update_bits_jmp_taken.value = 1
-    ittage.io_update_bits_mispred_mask_2.value = mispred
-    ittage.io_update_bits_meta.value = meta.dump_binary_str()
-    ittage.io_update_bits_full_target.value = int(target)
+    ittage.io_update_valid.xdata.value = 1
+    ittage.io_update_bits_pc.xdata.value = pc
+    ittage.io_update_bits_spec_info_folded_hist_hist_12_folded_hist.xdata.value = fh.get_t1_fh()
+    ittage.io_update_bits_spec_info_folded_hist_hist_14_folded_hist.xdata.value = fh.get_t2_fh()
+    ittage.io_update_bits_spec_info_folded_hist_hist_13_folded_hist.xdata.value, ittage.io_update_bits_spec_info_folded_hist_hist_4_folded_hist.xdata.value = fh.get_t3_fh()
+    ittage.io_update_bits_spec_info_folded_hist_hist_6_folded_hist.xdata.value, ittage.io_update_bits_spec_info_folded_hist_hist_2_folded_hist.xdata.value = fh.get_t4_fh()
+    ittage.io_update_bits_spec_info_folded_hist_hist_10_folded_hist.xdata.value, ittage.io_update_bits_spec_info_folded_hist_hist_3_folded_hist.xdata.value = fh.get_t5_fh()
+    ittage.io_update_bits_ftb_entry_isJalr.xdata.value = 1
+    ittage.io_update_bits_ftb_entry_isRet.xdata.value = 0
+    ittage.io_update_bits_ftb_entry_tailSlot_valid.xdata.value = 1
+    ittage.io_update_bits_ftb_entry_tailSlot_sharing.xdata.value = 0 # non-conditional jump
+    ittage.io_update_bits_ftb_entry_tailSlot_offset.xdata.value = cfi_idx
+    ittage.io_update_bits_cfi_idx_valid.xdata.value = 1
+    ittage.io_update_bits_cfi_idx_bits.xdata.value = cfi_idx
+    ittage.io_update_bits_jmp_taken.xdata.value = 1
+    ittage.io_update_bits_mispred_mask_2.xdata.value = mispred
+    ittage.io_update_bits_meta.xdata.value = meta.dump_binary_str()
+    ittage.io_update_bits_full_target.xdata.value = int(target)
     ittage.Step(1)
-    ittage.io_update_valid.value = 0
+    ittage.io_update_valid.xdata.value = 0
     ittage.Step(2)
     if debug == True:
         print("--------------------- ITTAGE Full Update End ---------------------\n\n")
@@ -320,7 +320,7 @@ def test_ittage_raw():
     drive_full_update(ittage, pc, folded_hists, target, cfi_idx, mispred, metas[0])
     metas.append(drive_full_pred(ittage, pc, ftb_target, folded_hists))
 
-    ittage.finalize()
+    ittage.Finish()
 
 
 if __name__ == "__main__":

tests/ITTAGE_useful/test_useful.py

@@ -105,7 +105,7 @@ def test_ittage_useful():
     run_test_useful(ittage, '100', '011')
     print('========================== test ITTAGE useful bit end ==========================')
 
-    ittage.finalize()
+    ittage.Finish()
 
 
 if __name__ == '__main__':