add ITTAGE alloc test

tests/ITTAGE_alloc/test_alloc.py

@@ -0,0 +1,103 @@
+import sys
+sys.path.append("../")
+import os
+os.sys.path.append(os.path.dirname(os.path.abspath(__file__)) + "/..")
+
+from ITTAGE_raw.test_raw import *
+
+import mlvp.funcov as fc
+from mlvp.reporter import set_func_coverage, set_line_coverage
+
+from UT_ITTage import *
+
+
+def init_set_all_useful(ittage: DUTITTage):
+    pc_vec = []
+    fh_vec = []
+    tables_vec = ['001', '010', '011', '100']
+    for i in range(0, 4):
+        pc = random.randint(0, 0x1ffffffffff)
+        ftb_target = 0x11111111
+        targets = [0x111ff11ff11, 0x122ff22ff22, 0x133ff33ff33]
+        folded_hists = FoldedHists()
+        folded_hists.reinit_random_gh()
+        cfi_idx = random.randint(0, 15) # 0~15
+        mispred = 1
+        metas = []
+        # generate a meta
+        metas.append(drive_full_pred(ittage, pc, ftb_target, folded_hists))
+        metas[0].check_provided('0').set_allocate_bits('000')
+        # mispred 1: allocat new table item, this time the item is set as provider
+        drive_full_update(ittage, pc, folded_hists, targets[0], cfi_idx, mispred, metas[0])
+        metas.append(drive_full_pred(ittage, pc, ftb_target, folded_hists))
+        metas[1].check_provided('1').check_provider('000').check_providerU('0')
+        # mispred 2: update with mispred set new provider in longest matched table, last item set as altprovider
+        metas[1].set_allocate_bits(tables_vec[i])
+        drive_full_update(ittage, pc, folded_hists, targets[1], cfi_idx, mispred, metas[1])
+        metas.append(drive_full_pred(ittage, pc, ftb_target, folded_hists))
+        metas[2].check_provided('1').check_provider(tables_vec[i]).check_providerU('0').check_providerCtr('10').check_providerTarget(targets[1])
+        metas[2].check_altProvided('1').check_altProviderCtr('01').check_altProviderTarget(targets[0])
+        # provider and altProvider have different targets, correct prediction from provider should set providerU to 1'b1
+        mispred=0
+        metas[2].set_allocate_valid('0')
+        drive_full_update(ittage, pc, folded_hists, targets[1], cfi_idx, mispred, metas[2])
+        metas.append(drive_full_pred(ittage, pc, ftb_target, folded_hists))
+        metas[3].check_provided('1').check_provider(tables_vec[i]).check_providerU('1').check_providerCtr('11').check_providerTarget(targets[1])
+        metas[3].check_altProvided('1').check_altProviderTarget(targets[0])
+        # record
+        pc_vec.append(pc)
+        fh_vec.append(folded_hists)
+    return pc_vec, fh_vec
+
+
+def check_all_useful(ittage: DUTITTage, u: str, pc_vec, fh_vec):
+    assert(u=='0' or u=='1')
+    ftb_target = 0x11111111
+    for i in range(0, 4):
+        meta = drive_full_pred(ittage, pc_vec[i], ftb_target, fh_vec[i])
+        meta.check_providerU(u)
+
+
+def run_test_tick_ctr(ittage: DUTITTage):
+    # basic info
+    pc = random.randint(0, 0x1ffffffffff)
+    ftb_target = 0x11111111
+    target = random.randint(0, 0x1ffffffffff)
+    folded_hists = FoldedHists()
+    folded_hists.reinit_random_gh()
+    cfi_idx = random.randint(0, 15) # 0~15
+    mispred = 1
+    meta = drive_full_pred(ittage, pc, ftb_target, folded_hists)
+    meta.set_allocate_valid('0')
+
+    for k in range(0, 1):
+        print(f'-------------- LOOP-{k}:')
+        # Initialize useful bit to 1 in table-1~table~4
+        print('-------------- initialize useful bit to 1 in table-1 ~ table-4 --------------')
+        pc_vec, fh_vec = init_set_all_useful(ittage)
+
+        print('-------------- increase tickCtr to 0xff --------------')
+        for i in range(0, 255):
+            if i == 254:
+                check_all_useful(ittage, '1', pc_vec, fh_vec)
+            target = random.randint(0, 0x1ffffffffff)
+            drive_full_update(ittage, pc, folded_hists, target, cfi_idx, mispred, meta)
+
+        print('-------------- check cleared useful bits --------------')
+        # check useful all cleared to 0
+        check_all_useful(ittage, '0', pc_vec, fh_vec)
+
+
+def test_ittage_alloc():
+     # test tickCtr
+    ittage = DUTITTage(waveform_filename='ittage-alloc.fst', coverage_filename='ittage-alloc.dat')
+    reset_init(ittage)
+
+    print('========================== test ITTAGE tickCtr ==========================')
+    run_test_tick_ctr(ittage)
+    print('========================== test ITTAGE tickCtr end ==========================')
+
+    ittage.finalize()
+
+if __name__ == '__main__':
+    test_ittage_alloc()