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env-xs-ov-00-bpu
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add bpu top module

This commit is contained in:
Makiras 2024-08-14 13:18:22 +08:00
parent 2d02a12610
commit 5ff250c113
83 changed files with 72286 additions and 0 deletions
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3
Makefile
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@ -37,6 +37,9 @@ ras:
ittage:
make -f ./mk/ITTAGE.mk ittage
bputop:
make -f ./mk/BPUTop.mk BPUTop
filter:
cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'"

45
mk/BPUTop.mk Normal file
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@ -0,0 +1,45 @@
TOP_ENTRY := ./rtl/BPUTop/Predictor.sv
TOP_FILES := ./rtl/BPUTop.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_BPUTop
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := --verbose
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w BPUTop.fst
endif
endif
_WAVEFORM ?=
BPUTop:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker export ${TOP_ENTRY} --fs ${TOP_FILES} --lang ${TL} -c\
--tdir ${TARGET} ${_WAVEFORM} ${_EXAMPLE} ${_VERBOSE}

33
parse_relay.sh Executable file
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@ -0,0 +1,33 @@
#!/bin/zsh
## 初始文件名
filename="$1"
# 用于存储已经处理过的文件，避免重复处理
declare -A processed_files
# 递归查找依赖模块的函数
find_dependencies() {
# 查看$1是否在数组中
if [ -n "${processed_files[$1]}" ]; then
return
fi
# 添加文件到已处理列表
processed_files[$1]=$1
# 查找文件中的依赖模块
grep -E '^\s*[a-zA-Z0-9_]+\s+[a-zA-Z0-9_]+\s* \(' "$1" | awk '{print $1}' | uniq | while read -r module; do
# 递归查找模块的依赖
if [ -f "${module}.sv" ]; then
find_dependencies "${module}.sv"
elif [ -f "${module}.v" ]; then
find_dependencies "${module}.v"
fi
done
}
# 开始查找依赖
find_dependencies "$filename"
# 输出所有查找到的文件
echo ${processed_files[@]}

79
rtl/BPUTop.txt Normal file
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@ -0,0 +1,79 @@
./rtl/BPUTop/DelayN_4.sv
./rtl/BPUTop/ITTageTable_4.sv
./rtl/BPUTop/SRAMTemplate_39.sv
./rtl/BPUTop/PriorityMuxModule_4.sv
./rtl/BPUTop/array_0_0.sv
./rtl/BPUTop/data_mem_8x4.sv
./rtl/BPUTop/WrBypass_32.sv
./rtl/BPUTop/array_8.sv
./rtl/BPUTop/array_6_ext.v
./rtl/BPUTop/array_6.sv
./rtl/BPUTop/Folded1WDataModuleTemplate_2.sv
./rtl/BPUTop/array_3.sv
./rtl/BPUTop/DelayNWithValid_1.sv
./rtl/BPUTop/array_5_ext.v
./rtl/BPUTop/PriorityMuxModule_20.sv
./rtl/BPUTop/ITTage.sv
./rtl/BPUTop/WrBypass_41.sv
./rtl/BPUTop/ITTageTable_1.sv
./rtl/BPUTop/data_16x16.sv
./rtl/BPUTop/DelayN_2.sv
./rtl/BPUTop/Tage_SC.sv
./rtl/BPUTop/SRAMTemplate_15.sv
./rtl/BPUTop/data_32x16.sv
./rtl/BPUTop/DelayN_1.sv
./rtl/BPUTop/CAMTemplate_32.sv
./rtl/BPUTop/RAS.sv
./rtl/BPUTop/TageTable_2.sv
./rtl/BPUTop/data_mem_0_8x3.sv
./rtl/BPUTop/SRAMTemplate_34.sv
./rtl/BPUTop/SRAMTemplate_35.sv
./rtl/BPUTop/WrBypass_33.sv
./rtl/BPUTop/DelayNWithValid.sv
./rtl/BPUTop/PriorityMuxModule.sv
./rtl/BPUTop/PriorityMuxModule_8.sv
./rtl/BPUTop/SCTable.sv
./rtl/BPUTop/CAMTemplate.sv
./rtl/BPUTop/SCTable_1.sv
./rtl/BPUTop/FTB.sv
./rtl/BPUTop/FTBBank.sv
./rtl/BPUTop/WrBypass.sv
./rtl/BPUTop/TageTable_1.sv
./rtl/BPUTop/array_7_ext.v
./rtl/BPUTop/SRAMTemplate_14.sv
./rtl/BPUTop/FauFTBWay.sv
./rtl/BPUTop/data_mem_0_4x2.sv
./rtl/BPUTop/SRAMTemplate_43.sv
./rtl/BPUTop/RASStack.sv
./rtl/BPUTop/CAMTemplate_33.sv
./rtl/BPUTop/array_4_ext.v
./rtl/BPUTop/Predictor.sv
./rtl/BPUTop/array_4.sv
./rtl/BPUTop/SCTable_3.sv
./rtl/BPUTop/ITTageTable.sv
./rtl/BPUTop/CAMTemplate_43.sv
./rtl/BPUTop/TageTable_3.sv
./rtl/BPUTop/PriorityMuxModule_16.sv
./rtl/BPUTop/array_0_0_ext.v
./rtl/BPUTop/CAMTemplate_41.sv
./rtl/BPUTop/PriorityMuxModule_12.sv
./rtl/BPUTop/array_8_ext.v
./rtl/BPUTop/array_3_ext.v
./rtl/BPUTop/array_7.sv
./rtl/BPUTop/TageBTable.sv
./rtl/BPUTop/FoldedSRAMTemplate_1.sv
./rtl/BPUTop/FoldedSRAMTemplate_20.sv
./rtl/BPUTop/ITTageTable_2.sv
./rtl/BPUTop/WrBypass_43.sv
./rtl/BPUTop/FoldedSRAMTemplate_21.sv
./rtl/BPUTop/array_5.sv
./rtl/BPUTop/FoldedSRAMTemplate_25.sv
./rtl/BPUTop/Folded1WDataModuleTemplate.sv
./rtl/BPUTop/data_mem_16x12.sv
./rtl/BPUTop/FauFTB.sv
./rtl/BPUTop/SRAMTemplate_13.sv
./rtl/BPUTop/ITTageTable_3.sv
./rtl/BPUTop/Composer.sv
./rtl/BPUTop/FoldedSRAMTemplate.sv
./rtl/BPUTop/TageTable.sv
./rtl/BPUTop/SCTable_2.sv

136
rtl/BPUTop/CAMTemplate.sv Normal file
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@ -0,0 +1,136 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate(
input clock,
input [8:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
input io_w_valid,
input [8:0] io_w_bits_data_idx,
input [2:0] io_w_bits_index
);
reg [8:0] array_0;
reg [8:0] array_1;
reg [8:0] array_2;
reg [8:0] array_3;
reg [8:0] array_4;
reg [8:0] array_5;
reg [8:0] array_6;
reg [8:0] array_7;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_7 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
array_0 = _RANDOM[2'h0][8:0];
array_1 = _RANDOM[2'h0][17:9];
array_2 = _RANDOM[2'h0][26:18];
array_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][3:0]};
array_4 = _RANDOM[2'h1][12:4];
array_5 = _RANDOM[2'h1][21:13];
array_6 = _RANDOM[2'h1][30:22];
array_7 = {_RANDOM[2'h1][31], _RANDOM[2'h2][7:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
endmodule

136
rtl/BPUTop/CAMTemplate_32.sv Normal file
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@ -0,0 +1,136 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_32(
input clock,
input [10:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
input io_w_valid,
input [10:0] io_w_bits_data_idx,
input [2:0] io_w_bits_index
);
reg [10:0] array_0;
reg [10:0] array_1;
reg [10:0] array_2;
reg [10:0] array_3;
reg [10:0] array_4;
reg [10:0] array_5;
reg [10:0] array_6;
reg [10:0] array_7;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 3'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 3'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_7 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
array_0 = _RANDOM[2'h0][10:0];
array_1 = _RANDOM[2'h0][21:11];
array_2 = {_RANDOM[2'h0][31:22], _RANDOM[2'h1][0]};
array_3 = _RANDOM[2'h1][11:1];
array_4 = _RANDOM[2'h1][22:12];
array_5 = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][1:0]};
array_6 = _RANDOM[2'h2][12:2];
array_7 = _RANDOM[2'h2][23:13];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
endmodule

184
rtl/BPUTop/CAMTemplate_33.sv Normal file
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@ -0,0 +1,184 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_33(
input clock,
input [7:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
output io_r_resp_0_4,
output io_r_resp_0_5,
output io_r_resp_0_6,
output io_r_resp_0_7,
output io_r_resp_0_8,
output io_r_resp_0_9,
output io_r_resp_0_10,
output io_r_resp_0_11,
output io_r_resp_0_12,
output io_r_resp_0_13,
output io_r_resp_0_14,
output io_r_resp_0_15,
input io_w_valid,
input [7:0] io_w_bits_data_idx,
input [3:0] io_w_bits_index
);
reg [7:0] array_0;
reg [7:0] array_1;
reg [7:0] array_2;
reg [7:0] array_3;
reg [7:0] array_4;
reg [7:0] array_5;
reg [7:0] array_6;
reg [7:0] array_7;
reg [7:0] array_8;
reg [7:0] array_9;
reg [7:0] array_10;
reg [7:0] array_11;
reg [7:0] array_12;
reg [7:0] array_13;
reg [7:0] array_14;
reg [7:0] array_15;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 4'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h3)
array_3 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h4)
array_4 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h5)
array_5 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h6)
array_6 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h7)
array_7 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h8)
array_8 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'h9)
array_9 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hA)
array_10 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hB)
array_11 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hC)
array_12 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hD)
array_13 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 4'hE)
array_14 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_15 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
array_0 = _RANDOM[2'h0][7:0];
array_1 = _RANDOM[2'h0][15:8];
array_2 = _RANDOM[2'h0][23:16];
array_3 = _RANDOM[2'h0][31:24];
array_4 = _RANDOM[2'h1][7:0];
array_5 = _RANDOM[2'h1][15:8];
array_6 = _RANDOM[2'h1][23:16];
array_7 = _RANDOM[2'h1][31:24];
array_8 = _RANDOM[2'h2][7:0];
array_9 = _RANDOM[2'h2][15:8];
array_10 = _RANDOM[2'h2][23:16];
array_11 = _RANDOM[2'h2][31:24];
array_12 = _RANDOM[2'h3][7:0];
array_13 = _RANDOM[2'h3][15:8];
array_14 = _RANDOM[2'h3][23:16];
array_15 = _RANDOM[2'h3][31:24];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
assign io_r_resp_0_4 = io_r_req_0_idx == array_4;
assign io_r_resp_0_5 = io_r_req_0_idx == array_5;
assign io_r_resp_0_6 = io_r_req_0_idx == array_6;
assign io_r_resp_0_7 = io_r_req_0_idx == array_7;
assign io_r_resp_0_8 = io_r_req_0_idx == array_8;
assign io_r_resp_0_9 = io_r_req_0_idx == array_9;
assign io_r_resp_0_10 = io_r_req_0_idx == array_10;
assign io_r_resp_0_11 = io_r_req_0_idx == array_11;
assign io_r_resp_0_12 = io_r_req_0_idx == array_12;
assign io_r_resp_0_13 = io_r_req_0_idx == array_13;
assign io_r_resp_0_14 = io_r_req_0_idx == array_14;
assign io_r_resp_0_15 = io_r_req_0_idx == array_15;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_41(
input clock,
input [7:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
input io_w_valid,
input [7:0] io_w_bits_data_idx,
input [1:0] io_w_bits_index
);
reg [7:0] array_0;
reg [7:0] array_1;
reg [7:0] array_2;
reg [7:0] array_3;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_3 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0];
array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8];
array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16];
array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
endmodule

112
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_43(
input clock,
input [8:0] io_r_req_0_idx,
output io_r_resp_0_0,
output io_r_resp_0_1,
output io_r_resp_0_2,
output io_r_resp_0_3,
input io_w_valid,
input [8:0] io_w_bits_data_idx,
input [1:0] io_w_bits_index
);
reg [8:0] array_0;
reg [8:0] array_1;
reg [8:0] array_2;
reg [8:0] array_3;
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0)
array_0 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h1)
array_1 <= io_w_bits_data_idx;
if (io_w_valid & io_w_bits_index == 2'h2)
array_2 <= io_w_bits_data_idx;
if (io_w_valid & (&io_w_bits_index))
array_3 <= io_w_bits_data_idx;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
array_0 = _RANDOM[1'h0][8:0];
array_1 = _RANDOM[1'h0][17:9];
array_2 = _RANDOM[1'h0][26:18];
array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0;
assign io_r_resp_0_1 = io_r_req_0_idx == array_1;
assign io_r_resp_0_2 = io_r_req_0_idx == array_2;
assign io_r_resp_0_3 = io_r_req_0_idx == array_3;
endmodule

2426
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107
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayNWithValid(
input clock,
input reset,
input [40:0] io_in_bits,
input io_in_valid,
output [40:0] io_out_bits
);
reg valid_REG;
reg [40:0] data;
reg [40:0] res_bits;
always @(posedge clock or posedge reset) begin
if (reset)
valid_REG <= 1'h0;
else
valid_REG <= io_in_valid;
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_in_valid)
data <= io_in_bits;
if (valid_REG)
res_bits <= data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
valid_REG = _RANDOM[2'h0][0];
data = {_RANDOM[2'h0][31:1], _RANDOM[2'h1][9:0]};
res_bits = {_RANDOM[2'h1][31:11], _RANDOM[2'h2][19:0]};
`endif // RANDOMIZE_REG_INIT
if (reset)
valid_REG = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_bits = res_bits;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayNWithValid_1(
input clock,
input reset,
input io_in_bits_valid,
input [3:0] io_in_bits_brSlots_0_offset,
input [11:0] io_in_bits_brSlots_0_lower,
input [1:0] io_in_bits_brSlots_0_tarStat,
input io_in_bits_brSlots_0_sharing,
input io_in_bits_brSlots_0_valid,
input [3:0] io_in_bits_tailSlot_offset,
input [19:0] io_in_bits_tailSlot_lower,
input [1:0] io_in_bits_tailSlot_tarStat,
input io_in_bits_tailSlot_sharing,
input io_in_bits_tailSlot_valid,
input [3:0] io_in_bits_pftAddr,
input io_in_bits_carry,
input io_in_bits_isCall,
input io_in_bits_isRet,
input io_in_bits_isJalr,
input io_in_bits_last_may_be_rvi_call,
input io_in_bits_always_taken_0,
input io_in_bits_always_taken_1,
input io_in_valid,
output io_out_bits_valid,
output [3:0] io_out_bits_brSlots_0_offset,
output [11:0] io_out_bits_brSlots_0_lower,
output [1:0] io_out_bits_brSlots_0_tarStat,
output io_out_bits_brSlots_0_sharing,
output io_out_bits_brSlots_0_valid,
output [3:0] io_out_bits_tailSlot_offset,
output [19:0] io_out_bits_tailSlot_lower,
output [1:0] io_out_bits_tailSlot_tarStat,
output io_out_bits_tailSlot_sharing,
output io_out_bits_tailSlot_valid,
output [3:0] io_out_bits_pftAddr,
output io_out_bits_carry,
output io_out_bits_isCall,
output io_out_bits_isRet,
output io_out_bits_isJalr,
output io_out_bits_last_may_be_rvi_call,
output io_out_bits_always_taken_0,
output io_out_bits_always_taken_1
);
reg valid_REG;
reg data_valid;
reg [3:0] data_brSlots_0_offset;
reg [11:0] data_brSlots_0_lower;
reg [1:0] data_brSlots_0_tarStat;
reg data_brSlots_0_sharing;
reg data_brSlots_0_valid;
reg [3:0] data_tailSlot_offset;
reg [19:0] data_tailSlot_lower;
reg [1:0] data_tailSlot_tarStat;
reg data_tailSlot_sharing;
reg data_tailSlot_valid;
reg [3:0] data_pftAddr;
reg data_carry;
reg data_isCall;
reg data_isRet;
reg data_isJalr;
reg data_last_may_be_rvi_call;
reg data_always_taken_0;
reg data_always_taken_1;
reg res_bits_valid;
reg [3:0] res_bits_brSlots_0_offset;
reg [11:0] res_bits_brSlots_0_lower;
reg [1:0] res_bits_brSlots_0_tarStat;
reg res_bits_brSlots_0_sharing;
reg res_bits_brSlots_0_valid;
reg [3:0] res_bits_tailSlot_offset;
reg [19:0] res_bits_tailSlot_lower;
reg [1:0] res_bits_tailSlot_tarStat;
reg res_bits_tailSlot_sharing;
reg res_bits_tailSlot_valid;
reg [3:0] res_bits_pftAddr;
reg res_bits_carry;
reg res_bits_isCall;
reg res_bits_isRet;
reg res_bits_isJalr;
reg res_bits_last_may_be_rvi_call;
reg res_bits_always_taken_0;
reg res_bits_always_taken_1;
always @(posedge clock or posedge reset) begin
if (reset)
valid_REG <= 1'h0;
else
valid_REG <= io_in_valid;
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_in_valid) begin
data_valid <= io_in_bits_valid;
data_brSlots_0_offset <= io_in_bits_brSlots_0_offset;
data_brSlots_0_lower <= io_in_bits_brSlots_0_lower;
data_brSlots_0_tarStat <= io_in_bits_brSlots_0_tarStat;
data_brSlots_0_sharing <= io_in_bits_brSlots_0_sharing;
data_brSlots_0_valid <= io_in_bits_brSlots_0_valid;
data_tailSlot_offset <= io_in_bits_tailSlot_offset;
data_tailSlot_lower <= io_in_bits_tailSlot_lower;
data_tailSlot_tarStat <= io_in_bits_tailSlot_tarStat;
data_tailSlot_sharing <= io_in_bits_tailSlot_sharing;
data_tailSlot_valid <= io_in_bits_tailSlot_valid;
data_pftAddr <= io_in_bits_pftAddr;
data_carry <= io_in_bits_carry;
data_isCall <= io_in_bits_isCall;
data_isRet <= io_in_bits_isRet;
data_isJalr <= io_in_bits_isJalr;
data_last_may_be_rvi_call <= io_in_bits_last_may_be_rvi_call;
data_always_taken_0 <= io_in_bits_always_taken_0;
data_always_taken_1 <= io_in_bits_always_taken_1;
end
if (valid_REG) begin
res_bits_valid <= data_valid;
res_bits_brSlots_0_offset <= data_brSlots_0_offset;
res_bits_brSlots_0_lower <= data_brSlots_0_lower;
res_bits_brSlots_0_tarStat <= data_brSlots_0_tarStat;
res_bits_brSlots_0_sharing <= data_brSlots_0_sharing;
res_bits_brSlots_0_valid <= data_brSlots_0_valid;
res_bits_tailSlot_offset <= data_tailSlot_offset;
res_bits_tailSlot_lower <= data_tailSlot_lower;
res_bits_tailSlot_tarStat <= data_tailSlot_tarStat;
res_bits_tailSlot_sharing <= data_tailSlot_sharing;
res_bits_tailSlot_valid <= data_tailSlot_valid;
res_bits_pftAddr <= data_pftAddr;
res_bits_carry <= data_carry;
res_bits_isCall <= data_isCall;
res_bits_isRet <= data_isRet;
res_bits_isJalr <= data_isJalr;
res_bits_last_may_be_rvi_call <= data_last_may_be_rvi_call;
res_bits_always_taken_0 <= data_always_taken_0;
res_bits_always_taken_1 <= data_always_taken_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
valid_REG = _RANDOM[2'h0][0];
data_valid = _RANDOM[2'h0][1];
data_brSlots_0_offset = _RANDOM[2'h0][5:2];
data_brSlots_0_lower = _RANDOM[2'h0][17:6];
data_brSlots_0_tarStat = _RANDOM[2'h0][19:18];
data_brSlots_0_sharing = _RANDOM[2'h0][20];
data_brSlots_0_valid = _RANDOM[2'h0][21];
data_tailSlot_offset = _RANDOM[2'h0][25:22];
data_tailSlot_lower = {_RANDOM[2'h0][31:26], _RANDOM[2'h1][13:0]};
data_tailSlot_tarStat = _RANDOM[2'h1][15:14];
data_tailSlot_sharing = _RANDOM[2'h1][16];
data_tailSlot_valid = _RANDOM[2'h1][17];
data_pftAddr = _RANDOM[2'h1][21:18];
data_carry = _RANDOM[2'h1][22];
data_isCall = _RANDOM[2'h1][23];
data_isRet = _RANDOM[2'h1][24];
data_isJalr = _RANDOM[2'h1][25];
data_last_may_be_rvi_call = _RANDOM[2'h1][26];
data_always_taken_0 = _RANDOM[2'h1][27];
data_always_taken_1 = _RANDOM[2'h1][28];
res_bits_valid = _RANDOM[2'h1][30];
res_bits_brSlots_0_offset = {_RANDOM[2'h1][31], _RANDOM[2'h2][2:0]};
res_bits_brSlots_0_lower = _RANDOM[2'h2][14:3];
res_bits_brSlots_0_tarStat = _RANDOM[2'h2][16:15];
res_bits_brSlots_0_sharing = _RANDOM[2'h2][17];
res_bits_brSlots_0_valid = _RANDOM[2'h2][18];
res_bits_tailSlot_offset = _RANDOM[2'h2][22:19];
res_bits_tailSlot_lower = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][10:0]};
res_bits_tailSlot_tarStat = _RANDOM[2'h3][12:11];
res_bits_tailSlot_sharing = _RANDOM[2'h3][13];
res_bits_tailSlot_valid = _RANDOM[2'h3][14];
res_bits_pftAddr = _RANDOM[2'h3][18:15];
res_bits_carry = _RANDOM[2'h3][19];
res_bits_isCall = _RANDOM[2'h3][20];
res_bits_isRet = _RANDOM[2'h3][21];
res_bits_isJalr = _RANDOM[2'h3][22];
res_bits_last_may_be_rvi_call = _RANDOM[2'h3][23];
res_bits_always_taken_0 = _RANDOM[2'h3][24];
res_bits_always_taken_1 = _RANDOM[2'h3][25];
`endif // RANDOMIZE_REG_INIT
if (reset)
valid_REG = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_bits_valid = res_bits_valid;
assign io_out_bits_brSlots_0_offset = res_bits_brSlots_0_offset;
assign io_out_bits_brSlots_0_lower = res_bits_brSlots_0_lower;
assign io_out_bits_brSlots_0_tarStat = res_bits_brSlots_0_tarStat;
assign io_out_bits_brSlots_0_sharing = res_bits_brSlots_0_sharing;
assign io_out_bits_brSlots_0_valid = res_bits_brSlots_0_valid;
assign io_out_bits_tailSlot_offset = res_bits_tailSlot_offset;
assign io_out_bits_tailSlot_lower = res_bits_tailSlot_lower;
assign io_out_bits_tailSlot_tarStat = res_bits_tailSlot_tarStat;
assign io_out_bits_tailSlot_sharing = res_bits_tailSlot_sharing;
assign io_out_bits_tailSlot_valid = res_bits_tailSlot_valid;
assign io_out_bits_pftAddr = res_bits_pftAddr;
assign io_out_bits_carry = res_bits_carry;
assign io_out_bits_isCall = res_bits_isCall;
assign io_out_bits_isRet = res_bits_isRet;
assign io_out_bits_isJalr = res_bits_isJalr;
assign io_out_bits_last_may_be_rvi_call = res_bits_last_may_be_rvi_call;
assign io_out_bits_always_taken_0 = res_bits_always_taken_0;
assign io_out_bits_always_taken_1 = res_bits_always_taken_1;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_1(
input clock,
input io_in_ubtb_enable,
input io_in_btb_enable,
input io_in_tage_enable,
input io_in_sc_enable,
input io_in_ras_enable,
output io_out_ubtb_enable,
output io_out_btb_enable,
output io_out_tage_enable,
output io_out_sc_enable,
output io_out_ras_enable
);
reg REG_ubtb_enable;
reg REG_btb_enable;
reg REG_tage_enable;
reg REG_sc_enable;
reg REG_ras_enable;
always @(posedge clock) begin
REG_ubtb_enable <= io_in_ubtb_enable;
REG_btb_enable <= io_in_btb_enable;
REG_tage_enable <= io_in_tage_enable;
REG_sc_enable <= io_in_sc_enable;
REG_ras_enable <= io_in_ras_enable;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
REG_ubtb_enable = _RANDOM[/*Zero width*/ 1'b0][0];
REG_btb_enable = _RANDOM[/*Zero width*/ 1'b0][1];
REG_tage_enable = _RANDOM[/*Zero width*/ 1'b0][3];
REG_sc_enable = _RANDOM[/*Zero width*/ 1'b0][4];
REG_ras_enable = _RANDOM[/*Zero width*/ 1'b0][5];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out_ubtb_enable = REG_ubtb_enable;
assign io_out_btb_enable = REG_btb_enable;
assign io_out_tage_enable = REG_tage_enable;
assign io_out_sc_enable = REG_sc_enable;
assign io_out_ras_enable = REG_ras_enable;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_2(
input clock,
input [35:0] io_in,
output [35:0] io_out
);
reg [35:0] REG;
reg [35:0] REG_1;
reg [35:0] REG_2;
reg [35:0] REG_3;
reg [35:0] REG_4;
always @(posedge clock) begin
REG <= io_in;
REG_1 <= REG;
REG_2 <= REG_1;
REG_3 <= REG_2;
REG_4 <= REG_3;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
REG = {_RANDOM[3'h0], _RANDOM[3'h1][3:0]};
REG_1 = {_RANDOM[3'h1][31:4], _RANDOM[3'h2][7:0]};
REG_2 = {_RANDOM[3'h2][31:8], _RANDOM[3'h3][11:0]};
REG_3 = {_RANDOM[3'h3][31:12], _RANDOM[3'h4][15:0]};
REG_4 = {_RANDOM[3'h4][31:16], _RANDOM[3'h5][19:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_4;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module DelayN_4(
input clock,
input io_in,
output io_out
);
reg REG;
reg REG_1;
always @(posedge clock) begin
REG <= io_in;
REG_1 <= REG;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
REG = _RANDOM[/*Zero width*/ 1'b0][0];
REG_1 = _RANDOM[/*Zero width*/ 1'b0][1];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_out = REG_1;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FauFTBWay(
input clock,
input reset,
input [15:0] io_req_tag,
output [3:0] io_resp_brSlots_0_offset,
output [11:0] io_resp_brSlots_0_lower,
output [1:0] io_resp_brSlots_0_tarStat,
output io_resp_brSlots_0_valid,
output [3:0] io_resp_tailSlot_offset,
output [19:0] io_resp_tailSlot_lower,
output [1:0] io_resp_tailSlot_tarStat,
output io_resp_tailSlot_sharing,
output io_resp_tailSlot_valid,
output [3:0] io_resp_pftAddr,
output io_resp_carry,
output io_resp_always_taken_0,
output io_resp_always_taken_1,
output io_resp_hit,
input [15:0] io_update_req_tag,
output io_update_hit,
input io_write_valid,
input [3:0] io_write_entry_brSlots_0_offset,
input [11:0] io_write_entry_brSlots_0_lower,
input [1:0] io_write_entry_brSlots_0_tarStat,
input io_write_entry_brSlots_0_valid,
input [3:0] io_write_entry_tailSlot_offset,
input [19:0] io_write_entry_tailSlot_lower,
input [1:0] io_write_entry_tailSlot_tarStat,
input io_write_entry_tailSlot_sharing,
input io_write_entry_tailSlot_valid,
input [3:0] io_write_entry_pftAddr,
input io_write_entry_carry,
input io_write_entry_always_taken_0,
input io_write_entry_always_taken_1,
input [15:0] io_write_tag
);
reg [3:0] data_brSlots_0_offset;
reg [11:0] data_brSlots_0_lower;
reg [1:0] data_brSlots_0_tarStat;
reg data_brSlots_0_valid;
reg [3:0] data_tailSlot_offset;
reg [19:0] data_tailSlot_lower;
reg [1:0] data_tailSlot_tarStat;
reg data_tailSlot_sharing;
reg data_tailSlot_valid;
reg [3:0] data_pftAddr;
reg data_carry;
reg data_always_taken_0;
reg data_always_taken_1;
reg [15:0] tag;
reg valid;
always @(posedge clock) begin
if (io_write_valid) begin
data_brSlots_0_offset <= io_write_entry_brSlots_0_offset;
data_brSlots_0_lower <= io_write_entry_brSlots_0_lower;
data_brSlots_0_tarStat <= io_write_entry_brSlots_0_tarStat;
data_brSlots_0_valid <= io_write_entry_brSlots_0_valid;
data_tailSlot_offset <= io_write_entry_tailSlot_offset;
data_tailSlot_lower <= io_write_entry_tailSlot_lower;
data_tailSlot_tarStat <= io_write_entry_tailSlot_tarStat;
data_tailSlot_sharing <= io_write_entry_tailSlot_sharing;
data_tailSlot_valid <= io_write_entry_tailSlot_valid;
data_pftAddr <= io_write_entry_pftAddr;
data_carry <= io_write_entry_carry;
data_always_taken_0 <= io_write_entry_always_taken_0;
data_always_taken_1 <= io_write_entry_always_taken_1;
tag <= io_write_tag;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
valid <= 1'h0;
else
valid <= io_write_valid & ~valid | valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
data_brSlots_0_offset = _RANDOM[2'h0][4:1];
data_brSlots_0_lower = _RANDOM[2'h0][16:5];
data_brSlots_0_tarStat = _RANDOM[2'h0][18:17];
data_brSlots_0_valid = _RANDOM[2'h0][20];
data_tailSlot_offset = _RANDOM[2'h0][24:21];
data_tailSlot_lower = {_RANDOM[2'h0][31:25], _RANDOM[2'h1][12:0]};
data_tailSlot_tarStat = _RANDOM[2'h1][14:13];
data_tailSlot_sharing = _RANDOM[2'h1][15];
data_tailSlot_valid = _RANDOM[2'h1][16];
data_pftAddr = _RANDOM[2'h1][20:17];
data_carry = _RANDOM[2'h1][21];
data_always_taken_0 = _RANDOM[2'h1][26];
data_always_taken_1 = _RANDOM[2'h1][27];
tag = {_RANDOM[2'h1][31:28], _RANDOM[2'h2][11:0]};
valid = _RANDOM[2'h2][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
valid = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_resp_brSlots_0_offset = data_brSlots_0_offset;
assign io_resp_brSlots_0_lower = data_brSlots_0_lower;
assign io_resp_brSlots_0_tarStat = data_brSlots_0_tarStat;
assign io_resp_brSlots_0_valid = data_brSlots_0_valid;
assign io_resp_tailSlot_offset = data_tailSlot_offset;
assign io_resp_tailSlot_lower = data_tailSlot_lower;
assign io_resp_tailSlot_tarStat = data_tailSlot_tarStat;
assign io_resp_tailSlot_sharing = data_tailSlot_sharing;
assign io_resp_tailSlot_valid = data_tailSlot_valid;
assign io_resp_pftAddr = data_pftAddr;
assign io_resp_carry = data_carry;
assign io_resp_always_taken_0 = data_always_taken_0;
assign io_resp_always_taken_1 = data_always_taken_1;
assign io_resp_hit = tag == io_req_tag & valid;
assign io_update_hit =
tag == io_update_req_tag & valid | io_write_tag == io_update_req_tag & io_write_valid;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate(
input clock,
input reset,
input io_ren_0,
input [7:0] io_raddr_0,
output io_rdata_0,
input io_wen,
input [7:0] io_waddr,
input io_wdata,
input io_resetEn
);
wire [15:0] _data_ext_R0_data;
reg doing_reset;
reg [3:0] resetRow;
reg [7:0] raddr_0;
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}};
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 4'h0;
end
else begin
doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset);
if (doing_reset)
resetRow <= 4'(resetRow + 4'h1);
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_ren_0)
raddr_0 <= io_raddr_0;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1];
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 4'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_16x16 data_ext (
.R0_addr (raddr_0[7:4]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[7:4]),
.W0_en (~doing_reset & io_wen),
.W0_clk (clock),
.W0_data ({16{io_wdata}}),
.W1_addr (resetRow),
.W1_en (doing_reset),
.W1_clk (clock),
.W1_data (16'h0)
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]];
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate_2(
input clock,
input reset,
input io_ren_0,
input [8:0] io_raddr_0,
output io_rdata_0,
input io_wen,
input [8:0] io_waddr,
input io_wdata,
input io_resetEn
);
wire [15:0] _data_ext_R0_data;
reg doing_reset;
reg [4:0] resetRow;
reg [8:0] raddr_0;
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}};
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 5'h0;
end
else begin
doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset);
if (doing_reset)
resetRow <= 5'(resetRow + 5'h1);
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_ren_0)
raddr_0 <= io_raddr_0;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1];
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 5'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_32x16 data_ext (
.R0_addr (raddr_0[8:4]),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[8:4]),
.W0_en (~doing_reset & io_wen),
.W0_clk (clock),
.W0_data ({16{io_wdata}}),
.W1_addr (resetRow),
.W1_en (doing_reset),
.W1_clk (clock),
.W1_data (16'h0)
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]];
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [10:0] io_r_req_bits_setIdx,
output io_r_resp_data_0,
output io_r_resp_data_1,
input io_w_req_valid,
input [10:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0,
input io_w_req_bits_data_1,
input [1:0] io_w_req_bits_waymask,
input extra_reset
);
wire _array_io_r_resp_data_0;
wire _array_io_r_resp_data_1;
wire _array_io_r_resp_data_2;
wire _array_io_r_resp_data_3;
wire _array_io_r_resp_data_4;
wire _array_io_r_resp_data_5;
wire _array_io_r_resp_data_6;
wire _array_io_r_resp_data_7;
wire _array_io_r_resp_data_8;
wire _array_io_r_resp_data_9;
wire _array_io_r_resp_data_10;
wire _array_io_r_resp_data_11;
wire _array_io_r_resp_data_12;
wire _array_io_r_resp_data_13;
wire _array_io_r_resp_data_14;
wire _array_io_r_resp_data_15;
reg [2:0] ridx;
reg holdRidx_last_r;
reg [2:0] holdRidx_hold_data;
wire [2:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
reg holdRidx_last_r_1;
reg [2:0] holdRidx_hold_data_1;
wire [2:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;
wire _wmask_T_3 = io_w_req_bits_setIdx[2:0] == 3'h0;
wire _wmask_T_9 = io_w_req_bits_setIdx[2:0] == 3'h1;
wire _wmask_T_15 = io_w_req_bits_setIdx[2:0] == 3'h2;
wire _wmask_T_21 = io_w_req_bits_setIdx[2:0] == 3'h3;
wire _wmask_T_27 = io_w_req_bits_setIdx[2:0] == 3'h4;
wire _wmask_T_33 = io_w_req_bits_setIdx[2:0] == 3'h5;
wire _wmask_T_39 = io_w_req_bits_setIdx[2:0] == 3'h6;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[2:0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
if (holdRidx_last_r_1)
holdRidx_hold_data_1 <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
holdRidx_last_r <= 1'h0;
holdRidx_last_r_1 <= 1'h0;
end
else begin
if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
if (io_r_req_valid | holdRidx_last_r_1)
holdRidx_last_r_1 <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][2:0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][3];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][6:4];
holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][7];
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
holdRidx_last_r = 1'h0;
holdRidx_last_r_1 = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_14 array (
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:3]),
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_r_resp_data_8 (_array_io_r_resp_data_8),
.io_r_resp_data_9 (_array_io_r_resp_data_9),
.io_r_resp_data_10 (_array_io_r_resp_data_10),
.io_r_resp_data_11 (_array_io_r_resp_data_11),
.io_r_resp_data_12 (_array_io_r_resp_data_12),
.io_r_resp_data_13 (_array_io_r_resp_data_13),
.io_r_resp_data_14 (_array_io_r_resp_data_14),
.io_r_resp_data_15 (_array_io_r_resp_data_15),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:3]),
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_data_8 (io_w_req_bits_data_0),
.io_w_req_bits_data_9 (io_w_req_bits_data_1),
.io_w_req_bits_data_10 (io_w_req_bits_data_0),
.io_w_req_bits_data_11 (io_w_req_bits_data_1),
.io_w_req_bits_data_12 (io_w_req_bits_data_0),
.io_w_req_bits_data_13 (io_w_req_bits_data_1),
.io_w_req_bits_data_14 (io_w_req_bits_data_0),
.io_w_req_bits_data_15 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[2:0])) & io_w_req_bits_waymask[0],
_wmask_T_39 & io_w_req_bits_waymask[1],
_wmask_T_39 & io_w_req_bits_waymask[0],
_wmask_T_33 & io_w_req_bits_waymask[1],
_wmask_T_33 & io_w_req_bits_waymask[0],
_wmask_T_27 & io_w_req_bits_waymask[1],
_wmask_T_27 & io_w_req_bits_waymask[0],
_wmask_T_21 & io_w_req_bits_waymask[1],
_wmask_T_21 & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]}),
.extra_reset (extra_reset)
);
assign io_r_resp_data_0 =
holdRidx == 3'h0 & _array_io_r_resp_data_0 | holdRidx == 3'h1
& _array_io_r_resp_data_2 | holdRidx == 3'h2 & _array_io_r_resp_data_4
| holdRidx == 3'h3 & _array_io_r_resp_data_6 | holdRidx == 3'h4
& _array_io_r_resp_data_8 | holdRidx == 3'h5 & _array_io_r_resp_data_10
| holdRidx == 3'h6 & _array_io_r_resp_data_12 | (&holdRidx)
& _array_io_r_resp_data_14;
assign io_r_resp_data_1 =
holdRidx_1 == 3'h0 & _array_io_r_resp_data_1 | holdRidx_1 == 3'h1
& _array_io_r_resp_data_3 | holdRidx_1 == 3'h2 & _array_io_r_resp_data_5
| holdRidx_1 == 3'h3 & _array_io_r_resp_data_7 | holdRidx_1 == 3'h4
& _array_io_r_resp_data_9 | holdRidx_1 == 3'h5 & _array_io_r_resp_data_11
| holdRidx_1 == 3'h6 & _array_io_r_resp_data_13 | (&holdRidx_1)
& _array_io_r_resp_data_15;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_1(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [7:0] io_r_resp_data_0_tag,
output [2:0] io_r_resp_data_0_ctr,
output io_r_resp_data_1_valid,
output [7:0] io_r_resp_data_1_tag,
output [2:0] io_r_resp_data_1_ctr,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [7:0] io_w_req_bits_data_0_tag,
input [2:0] io_w_req_bits_data_0_ctr,
input [7:0] io_w_req_bits_data_1_tag,
input [2:0] io_w_req_bits_data_1_ctr,
input [1:0] io_w_req_bits_waymask
);
SRAMTemplate_15 array (
.clock (clock),
.reset (reset),
.io_r_req_ready (io_r_req_ready),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_valid (io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (io_r_resp_data_1_ctr),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_1_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_1_ctr),
.io_w_req_bits_waymask (io_w_req_bits_waymask)
);
endmodule

180
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_20(
input clock,
input reset,
input io_r_req_valid,
input [10:0] io_r_req_bits_setIdx,
output [1:0] io_r_resp_data_0,
output [1:0] io_r_resp_data_1,
input io_w_req_valid,
input [10:0] io_w_req_bits_setIdx,
input [1:0] io_w_req_bits_data_0,
input [1:0] io_w_req_bits_data_1,
input [1:0] io_w_req_bits_waymask
);
wire [1:0] _array_io_r_resp_data_0;
wire [1:0] _array_io_r_resp_data_1;
wire [1:0] _array_io_r_resp_data_2;
wire [1:0] _array_io_r_resp_data_3;
wire [1:0] _array_io_r_resp_data_4;
wire [1:0] _array_io_r_resp_data_5;
wire [1:0] _array_io_r_resp_data_6;
wire [1:0] _array_io_r_resp_data_7;
reg [1:0] ridx;
reg holdRidx_last_r;
reg [1:0] holdRidx_hold_data;
wire [1:0] holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
reg holdRidx_last_r_1;
reg [1:0] holdRidx_hold_data_1;
wire [1:0] holdRidx_1 = holdRidx_last_r_1 ? ridx : holdRidx_hold_data_1;
wire _wmask_T_3 = io_w_req_bits_setIdx[1:0] == 2'h0;
wire _wmask_T_9 = io_w_req_bits_setIdx[1:0] == 2'h1;
wire _wmask_T_15 = io_w_req_bits_setIdx[1:0] == 2'h2;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[1:0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
if (holdRidx_last_r_1)
holdRidx_hold_data_1 <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
holdRidx_last_r <= 1'h0;
holdRidx_last_r_1 <= 1'h0;
end
else begin
if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
if (io_r_req_valid | holdRidx_last_r_1)
holdRidx_last_r_1 <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][1:0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][2];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][4:3];
holdRidx_last_r_1 = _RANDOM[/*Zero width*/ 1'b0][5];
holdRidx_hold_data_1 = _RANDOM[/*Zero width*/ 1'b0][7:6];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
holdRidx_last_r = 1'h0;
holdRidx_last_r_1 = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_34 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[10:2]),
.io_r_resp_data_0 (_array_io_r_resp_data_0),
.io_r_resp_data_1 (_array_io_r_resp_data_1),
.io_r_resp_data_2 (_array_io_r_resp_data_2),
.io_r_resp_data_3 (_array_io_r_resp_data_3),
.io_r_resp_data_4 (_array_io_r_resp_data_4),
.io_r_resp_data_5 (_array_io_r_resp_data_5),
.io_r_resp_data_6 (_array_io_r_resp_data_6),
.io_r_resp_data_7 (_array_io_r_resp_data_7),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[10:2]),
.io_w_req_bits_data_0 (io_w_req_bits_data_0),
.io_w_req_bits_data_1 (io_w_req_bits_data_1),
.io_w_req_bits_data_2 (io_w_req_bits_data_0),
.io_w_req_bits_data_3 (io_w_req_bits_data_1),
.io_w_req_bits_data_4 (io_w_req_bits_data_0),
.io_w_req_bits_data_5 (io_w_req_bits_data_1),
.io_w_req_bits_data_6 (io_w_req_bits_data_0),
.io_w_req_bits_data_7 (io_w_req_bits_data_1),
.io_w_req_bits_waymask
({(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[1],
(&(io_w_req_bits_setIdx[1:0])) & io_w_req_bits_waymask[0],
_wmask_T_15 & io_w_req_bits_waymask[1],
_wmask_T_15 & io_w_req_bits_waymask[0],
_wmask_T_9 & io_w_req_bits_waymask[1],
_wmask_T_9 & io_w_req_bits_waymask[0],
_wmask_T_3 & io_w_req_bits_waymask[1],
_wmask_T_3 & io_w_req_bits_waymask[0]})
);
assign io_r_resp_data_0 =
(holdRidx == 2'h0 ? _array_io_r_resp_data_0 : 2'h0)
| (holdRidx == 2'h1 ? _array_io_r_resp_data_2 : 2'h0)
| (holdRidx == 2'h2 ? _array_io_r_resp_data_4 : 2'h0)
| ((&holdRidx) ? _array_io_r_resp_data_6 : 2'h0);
assign io_r_resp_data_1 =
(holdRidx_1 == 2'h0 ? _array_io_r_resp_data_1 : 2'h0)
| (holdRidx_1 == 2'h1 ? _array_io_r_resp_data_3 : 2'h0)
| (holdRidx_1 == 2'h2 ? _array_io_r_resp_data_5 : 2'h0)
| ((&holdRidx_1) ? _array_io_r_resp_data_7 : 2'h0);
endmodule

90
rtl/BPUTop/FoldedSRAMTemplate_21.sv Normal file
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_21(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
SRAMTemplate_39 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_valid (io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (io_r_resp_data_0_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target)
);
endmodule

155
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_25(
input clock,
input reset,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
wire _array_io_r_resp_data_0_valid;
wire [8:0] _array_io_r_resp_data_0_tag;
wire [1:0] _array_io_r_resp_data_0_ctr;
wire [40:0] _array_io_r_resp_data_0_target;
wire _array_io_r_resp_data_1_valid;
wire [8:0] _array_io_r_resp_data_1_tag;
wire [1:0] _array_io_r_resp_data_1_ctr;
wire [40:0] _array_io_r_resp_data_1_target;
reg ridx;
reg holdRidx_last_r;
reg holdRidx_hold_data;
wire holdRidx = holdRidx_last_r ? ridx : holdRidx_hold_data;
always @(posedge clock) begin
if (io_r_req_valid)
ridx <= io_r_req_bits_setIdx[0];
if (holdRidx_last_r)
holdRidx_hold_data <= ridx;
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
holdRidx_last_r <= 1'h0;
else if (io_r_req_valid | holdRidx_last_r)
holdRidx_last_r <= io_r_req_valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ridx = _RANDOM[/*Zero width*/ 1'b0][0];
holdRidx_last_r = _RANDOM[/*Zero width*/ 1'b0][1];
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2];
`endif // RANDOMIZE_REG_INIT
if (reset)
holdRidx_last_r = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_43 array (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]),
.io_r_resp_data_0_valid (_array_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_array_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_array_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_array_io_r_resp_data_0_target),
.io_r_resp_data_1_valid (_array_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_array_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_array_io_r_resp_data_1_ctr),
.io_r_resp_data_1_target (_array_io_r_resp_data_1_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_target (io_w_req_bits_data_0_target),
.io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0])
);
assign io_r_resp_data_0_valid =
~holdRidx & _array_io_r_resp_data_0_valid | holdRidx & _array_io_r_resp_data_1_valid;
assign io_r_resp_data_0_tag =
(holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag)
| (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0);
assign io_r_resp_data_0_ctr =
(holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr)
| (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0);
assign io_r_resp_data_0_target =
(holdRidx ? 41'h0 : _array_io_r_resp_data_0_target)
| (holdRidx ? _array_io_r_resp_data_1_target : 41'h0);
endmodule

1269
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [3:0] io_update_folded_hist_hist_12_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [3:0] _GEN = io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
wire [6:0] _table_banks_1_io_r_req_bits_setIdx_T = {io_req_bits_pc[8:5], _GEN[3:1]};
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [3:0] _GEN_0 = io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist;
wire [7:0] update_idx = {io_update_pc[8:5], _GEN_0};
wire [8:0] update_tag =
{io_update_pc[17:14],
{io_update_pc[13], io_update_pc[12:9] ^ io_update_folded_hist_hist_12_folded_hist}
^ {io_update_folded_hist_hist_12_folded_hist, 1'h0}};
wire [6:0] update_idx_in_bank = {io_update_pc[8:5], _GEN_0[3:1]};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(_GEN_0[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & _GEN_0[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
{io_req_bits_pc[17:14],
{io_req_bits_pc[13],
io_req_bits_pc[12:9] ^ io_req_bits_folded_hist_hist_12_folded_hist}
^ {io_req_bits_folded_hist_hist_12_folded_hist, 1'h0}};
s1_bank_req_1h_0 <= ~(_GEN[0]);
s1_bank_req_1h_1 <= _GEN[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 ({io_req_bits_pc[8:5], _GEN}),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(_GEN[0])),
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_21 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & _GEN[0]),
.io_r_req_bits_setIdx (_table_banks_1_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_41 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

221
rtl/BPUTop/ITTageTable_1.sv Normal file
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@ -0,0 +1,221 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_1(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_14_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [7:0] s0_idx = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;
wire [8:0] update_tag =
{io_update_pc[17], io_update_pc[16:9] ^ io_update_folded_hist_hist_14_folded_hist}
^ {io_update_folded_hist_hist_14_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
{io_req_bits_pc[17],
io_req_bits_pc[16:9] ^ io_req_bits_folded_hist_hist_14_folded_hist}
^ {io_req_bits_folded_hist_hist_14_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][16:8];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][17];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][20];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_21 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[7:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[7:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_21 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[7:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[7:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_41 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_2.sv Normal file
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@ -0,0 +1,222 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_2(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_13_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_13_folded_hist,
input [7:0] io_update_folded_hist_hist_4_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_13_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_13_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_13_folded_hist
^ {io_update_folded_hist_hist_4_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_13_folded_hist
^ {io_req_bits_folded_hist_hist_4_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_3.sv Normal file
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@ -0,0 +1,222 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_3(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_6_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_6_folded_hist,
input [7:0] io_update_folded_hist_hist_2_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_6_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_6_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_6_folded_hist
^ {io_update_folded_hist_hist_2_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_6_folded_hist
^ {io_req_bits_folded_hist_hist_2_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

222
rtl/BPUTop/ITTageTable_4.sv Normal file
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@ -0,0 +1,222 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module ITTageTable_4(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [8:0] io_req_bits_folded_hist_hist_10_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist,
output io_resp_valid,
output [1:0] io_resp_bits_ctr,
output [1:0] io_resp_bits_u,
output [40:0] io_resp_bits_target,
input [40:0] io_update_pc,
input [8:0] io_update_folded_hist_hist_10_folded_hist,
input [7:0] io_update_folded_hist_hist_3_folded_hist,
input io_update_valid,
input io_update_correct,
input io_update_alloc,
input [1:0] io_update_oldCtr,
input io_update_uValid,
input io_update_u,
input io_update_reset_u,
input [40:0] io_update_target,
input [40:0] io_update_old_target
);
wire _resp_invalid_by_write_T_2;
wire _wrbypass_io_hit;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [8:0] _table_banks_1_io_r_resp_data_0_tag;
wire [1:0] _table_banks_1_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_1_io_r_resp_data_0_target;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [8:0] _table_banks_0_io_r_resp_data_0_tag;
wire [1:0] _table_banks_0_io_r_resp_data_0_ctr;
wire [40:0] _table_banks_0_io_r_resp_data_0_target;
wire _us_io_rdata_0;
wire [8:0] s0_idx = io_req_bits_pc[9:1] ^ io_req_bits_folded_hist_hist_10_folded_hist;
reg [8:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
wire [8:0] update_idx = io_update_pc[9:1] ^ io_update_folded_hist_hist_10_folded_hist;
wire [8:0] update_tag =
io_update_pc[18:10] ^ io_update_folded_hist_hist_10_folded_hist
^ {io_update_folded_hist_hist_3_folded_hist, 1'h0};
assign _resp_invalid_by_write_T_2 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1;
wire _s1_bank_has_write_on_this_req_WIRE_0 = io_update_valid & ~(update_idx[0]);
wire _s1_bank_has_write_on_this_req_WIRE_1 = io_update_valid & update_idx[0];
wire [1:0] old_ctr =
_wrbypass_io_hit ? _wrbypass_io_hit_data_0_bits : io_update_oldCtr;
wire update_wdata_ctr_oldSatNotTaken = old_ctr == 2'h0;
wire [1:0] update_wdata_ctr =
io_update_alloc
? 2'h2
: (&old_ctr) & io_update_correct
? 2'h3
: update_wdata_ctr_oldSatNotTaken & ~io_update_correct
? 2'h0
: io_update_correct ? 2'(old_ctr + 2'h1) : 2'(old_ctr - 2'h1);
wire [40:0] update_wdata_target =
io_update_alloc | update_wdata_ctr_oldSatNotTaken
? io_update_target
: io_update_old_target;
always @(posedge clock) begin
if (io_req_valid) begin
s1_tag <=
io_req_bits_pc[18:10] ^ io_req_bits_folded_hist_hist_10_folded_hist
^ {io_req_bits_folded_hist_hist_3_folded_hist, 1'h0};
s1_bank_req_1h_0 <= ~(s0_idx[0]);
s1_bank_req_1h_1 <= s0_idx[0];
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
s1_tag = _RANDOM[/*Zero width*/ 1'b0][17:9];
s1_bank_req_1h_0 = _RANDOM[/*Zero width*/ 1'b0][18];
s1_bank_req_1h_1 = _RANDOM[/*Zero width*/ 1'b0][19];
s1_bank_has_write_on_this_req_0 = _RANDOM[/*Zero width*/ 1'b0][20];
s1_bank_has_write_on_this_req_1 = _RANDOM[/*Zero width*/ 1'b0][21];
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
Folded1WDataModuleTemplate_2 us (
.clock (clock),
.reset (reset),
.io_ren_0 (io_req_valid),
.io_raddr_0 (s0_idx),
.io_rdata_0 (_us_io_rdata_0),
.io_wen (io_update_uValid),
.io_waddr (update_idx),
.io_wdata (io_update_u),
.io_resetEn (io_update_reset_u)
);
FoldedSRAMTemplate_25 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & ~(s0_idx[0])),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_0_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
FoldedSRAMTemplate_25 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid & s0_idx[0]),
.io_r_req_bits_setIdx (s0_idx[8:1]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_table_banks_1_io_r_resp_data_0_target),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[8:1]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (update_wdata_ctr),
.io_w_req_bits_data_0_target (update_wdata_target)
);
WrBypass_43 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (io_update_valid),
.io_write_idx (update_idx),
.io_write_data_0 (update_wdata_ctr),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits)
);
assign io_resp_valid =
(s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_valid | s1_bank_req_1h_1
& _table_banks_1_io_r_resp_data_0_valid)
& ((s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_tag : 9'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_tag : 9'h0)) == s1_tag
& ~_resp_invalid_by_write_T_2;
assign io_resp_bits_ctr =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 2'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 2'h0);
assign io_resp_bits_u = {1'h0, _us_io_rdata_0};
assign io_resp_bits_target =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_target : 41'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_target : 41'h0);
endmodule

33300
rtl/BPUTop/Predictor.sv Normal file
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80
rtl/BPUTop/PriorityMuxModule.sv Normal file
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@ -0,0 +1,80 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule(
input s2_target_sel,
input [40:0] s2_target_src,
input s1_target_sel,
input [40:0] s1_target_src,
input s3_target_sel,
input [40:0] s3_target_src,
input redirect_target_sel,
input [40:0] redirect_target_src,
input [40:0] stallPC_src,
output [40:0] out_res
);
assign out_res =
s2_target_sel
? s2_target_src
: s1_target_sel
? s1_target_src
: s3_target_sel
? s3_target_src
: redirect_target_sel ? redirect_target_src : stallPC_src;
endmodule

450
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_12(
input s2_AFHOB_sel,
input s2_AFHOB_src_afhob_5_bits_0,
input s2_AFHOB_src_afhob_5_bits_1,
input s2_AFHOB_src_afhob_5_bits_2,
input s2_AFHOB_src_afhob_5_bits_3,
input s2_AFHOB_src_afhob_4_bits_0,
input s2_AFHOB_src_afhob_4_bits_1,
input s2_AFHOB_src_afhob_4_bits_2,
input s2_AFHOB_src_afhob_4_bits_3,
input s2_AFHOB_src_afhob_3_bits_0,
input s2_AFHOB_src_afhob_3_bits_1,
input s2_AFHOB_src_afhob_3_bits_2,
input s2_AFHOB_src_afhob_3_bits_3,
input s2_AFHOB_src_afhob_2_bits_0,
input s2_AFHOB_src_afhob_2_bits_1,
input s2_AFHOB_src_afhob_2_bits_2,
input s2_AFHOB_src_afhob_2_bits_3,
input s2_AFHOB_src_afhob_1_bits_0,
input s2_AFHOB_src_afhob_1_bits_1,
input s2_AFHOB_src_afhob_1_bits_2,
input s2_AFHOB_src_afhob_1_bits_3,
input s2_AFHOB_src_afhob_0_bits_0,
input s2_AFHOB_src_afhob_0_bits_1,
input s2_AFHOB_src_afhob_0_bits_2,
input s2_AFHOB_src_afhob_0_bits_3,
input s1_AFHOB_sel,
input s1_AFHOB_src_afhob_5_bits_0,
input s1_AFHOB_src_afhob_5_bits_1,
input s1_AFHOB_src_afhob_5_bits_2,
input s1_AFHOB_src_afhob_5_bits_3,
input s1_AFHOB_src_afhob_4_bits_0,
input s1_AFHOB_src_afhob_4_bits_1,
input s1_AFHOB_src_afhob_4_bits_2,
input s1_AFHOB_src_afhob_4_bits_3,
input s1_AFHOB_src_afhob_3_bits_0,
input s1_AFHOB_src_afhob_3_bits_1,
input s1_AFHOB_src_afhob_3_bits_2,
input s1_AFHOB_src_afhob_3_bits_3,
input s1_AFHOB_src_afhob_2_bits_0,
input s1_AFHOB_src_afhob_2_bits_1,
input s1_AFHOB_src_afhob_2_bits_2,
input s1_AFHOB_src_afhob_2_bits_3,
input s1_AFHOB_src_afhob_1_bits_0,
input s1_AFHOB_src_afhob_1_bits_1,
input s1_AFHOB_src_afhob_1_bits_2,
input s1_AFHOB_src_afhob_1_bits_3,
input s1_AFHOB_src_afhob_0_bits_0,
input s1_AFHOB_src_afhob_0_bits_1,
input s1_AFHOB_src_afhob_0_bits_2,
input s1_AFHOB_src_afhob_0_bits_3,
input s3_AFHOB_sel,
input s3_AFHOB_src_afhob_5_bits_0,
input s3_AFHOB_src_afhob_5_bits_1,
input s3_AFHOB_src_afhob_5_bits_2,
input s3_AFHOB_src_afhob_5_bits_3,
input s3_AFHOB_src_afhob_4_bits_0,
input s3_AFHOB_src_afhob_4_bits_1,
input s3_AFHOB_src_afhob_4_bits_2,
input s3_AFHOB_src_afhob_4_bits_3,
input s3_AFHOB_src_afhob_3_bits_0,
input s3_AFHOB_src_afhob_3_bits_1,
input s3_AFHOB_src_afhob_3_bits_2,
input s3_AFHOB_src_afhob_3_bits_3,
input s3_AFHOB_src_afhob_2_bits_0,
input s3_AFHOB_src_afhob_2_bits_1,
input s3_AFHOB_src_afhob_2_bits_2,
input s3_AFHOB_src_afhob_2_bits_3,
input s3_AFHOB_src_afhob_1_bits_0,
input s3_AFHOB_src_afhob_1_bits_1,
input s3_AFHOB_src_afhob_1_bits_2,
input s3_AFHOB_src_afhob_1_bits_3,
input s3_AFHOB_src_afhob_0_bits_0,
input s3_AFHOB_src_afhob_0_bits_1,
input s3_AFHOB_src_afhob_0_bits_2,
input s3_AFHOB_src_afhob_0_bits_3,
input redirect_AFHOB_sel,
input redirect_AFHOB_src_afhob_5_bits_0,
input redirect_AFHOB_src_afhob_5_bits_1,
input redirect_AFHOB_src_afhob_5_bits_2,
input redirect_AFHOB_src_afhob_5_bits_3,
input redirect_AFHOB_src_afhob_4_bits_0,
input redirect_AFHOB_src_afhob_4_bits_1,
input redirect_AFHOB_src_afhob_4_bits_2,
input redirect_AFHOB_src_afhob_4_bits_3,
input redirect_AFHOB_src_afhob_3_bits_0,
input redirect_AFHOB_src_afhob_3_bits_1,
input redirect_AFHOB_src_afhob_3_bits_2,
input redirect_AFHOB_src_afhob_3_bits_3,
input redirect_AFHOB_src_afhob_2_bits_0,
input redirect_AFHOB_src_afhob_2_bits_1,
input redirect_AFHOB_src_afhob_2_bits_2,
input redirect_AFHOB_src_afhob_2_bits_3,
input redirect_AFHOB_src_afhob_1_bits_0,
input redirect_AFHOB_src_afhob_1_bits_1,
input redirect_AFHOB_src_afhob_1_bits_2,
input redirect_AFHOB_src_afhob_1_bits_3,
input redirect_AFHOB_src_afhob_0_bits_0,
input redirect_AFHOB_src_afhob_0_bits_1,
input redirect_AFHOB_src_afhob_0_bits_2,
input redirect_AFHOB_src_afhob_0_bits_3,
input stallAFHOB_src_afhob_5_bits_0,
input stallAFHOB_src_afhob_5_bits_1,
input stallAFHOB_src_afhob_5_bits_2,
input stallAFHOB_src_afhob_5_bits_3,
input stallAFHOB_src_afhob_4_bits_0,
input stallAFHOB_src_afhob_4_bits_1,
input stallAFHOB_src_afhob_4_bits_2,
input stallAFHOB_src_afhob_4_bits_3,
input stallAFHOB_src_afhob_3_bits_0,
input stallAFHOB_src_afhob_3_bits_1,
input stallAFHOB_src_afhob_3_bits_2,
input stallAFHOB_src_afhob_3_bits_3,
input stallAFHOB_src_afhob_2_bits_0,
input stallAFHOB_src_afhob_2_bits_1,
input stallAFHOB_src_afhob_2_bits_2,
input stallAFHOB_src_afhob_2_bits_3,
input stallAFHOB_src_afhob_1_bits_0,
input stallAFHOB_src_afhob_1_bits_1,
input stallAFHOB_src_afhob_1_bits_2,
input stallAFHOB_src_afhob_1_bits_3,
input stallAFHOB_src_afhob_0_bits_0,
input stallAFHOB_src_afhob_0_bits_1,
input stallAFHOB_src_afhob_0_bits_2,
input stallAFHOB_src_afhob_0_bits_3,
output out_res_afhob_5_bits_0,
output out_res_afhob_5_bits_1,
output out_res_afhob_5_bits_2,
output out_res_afhob_5_bits_3,
output out_res_afhob_4_bits_0,
output out_res_afhob_4_bits_1,
output out_res_afhob_4_bits_2,
output out_res_afhob_4_bits_3,
output out_res_afhob_3_bits_0,
output out_res_afhob_3_bits_1,
output out_res_afhob_3_bits_2,
output out_res_afhob_3_bits_3,
output out_res_afhob_2_bits_0,
output out_res_afhob_2_bits_1,
output out_res_afhob_2_bits_2,
output out_res_afhob_2_bits_3,
output out_res_afhob_1_bits_0,
output out_res_afhob_1_bits_1,
output out_res_afhob_1_bits_2,
output out_res_afhob_1_bits_3,
output out_res_afhob_0_bits_0,
output out_res_afhob_0_bits_1,
output out_res_afhob_0_bits_2,
output out_res_afhob_0_bits_3
);
assign out_res_afhob_5_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_0
: stallAFHOB_src_afhob_5_bits_0;
assign out_res_afhob_5_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_1
: stallAFHOB_src_afhob_5_bits_1;
assign out_res_afhob_5_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_2
: stallAFHOB_src_afhob_5_bits_2;
assign out_res_afhob_5_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_5_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_5_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_5_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_5_bits_3
: stallAFHOB_src_afhob_5_bits_3;
assign out_res_afhob_4_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_0
: stallAFHOB_src_afhob_4_bits_0;
assign out_res_afhob_4_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_1
: stallAFHOB_src_afhob_4_bits_1;
assign out_res_afhob_4_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_2
: stallAFHOB_src_afhob_4_bits_2;
assign out_res_afhob_4_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_4_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_4_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_4_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_4_bits_3
: stallAFHOB_src_afhob_4_bits_3;
assign out_res_afhob_3_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_0
: stallAFHOB_src_afhob_3_bits_0;
assign out_res_afhob_3_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_1
: stallAFHOB_src_afhob_3_bits_1;
assign out_res_afhob_3_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_2
: stallAFHOB_src_afhob_3_bits_2;
assign out_res_afhob_3_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_3_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_3_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_3_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_3_bits_3
: stallAFHOB_src_afhob_3_bits_3;
assign out_res_afhob_2_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_0
: stallAFHOB_src_afhob_2_bits_0;
assign out_res_afhob_2_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_1
: stallAFHOB_src_afhob_2_bits_1;
assign out_res_afhob_2_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_2
: stallAFHOB_src_afhob_2_bits_2;
assign out_res_afhob_2_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_2_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_2_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_2_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_2_bits_3
: stallAFHOB_src_afhob_2_bits_3;
assign out_res_afhob_1_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_0
: stallAFHOB_src_afhob_1_bits_0;
assign out_res_afhob_1_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_1
: stallAFHOB_src_afhob_1_bits_1;
assign out_res_afhob_1_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_2
: stallAFHOB_src_afhob_1_bits_2;
assign out_res_afhob_1_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_1_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_1_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_1_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_1_bits_3
: stallAFHOB_src_afhob_1_bits_3;
assign out_res_afhob_0_bits_0 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_0
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_0
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_0
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_0
: stallAFHOB_src_afhob_0_bits_0;
assign out_res_afhob_0_bits_1 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_1
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_1
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_1
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_1
: stallAFHOB_src_afhob_0_bits_1;
assign out_res_afhob_0_bits_2 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_2
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_2
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_2
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_2
: stallAFHOB_src_afhob_0_bits_2;
assign out_res_afhob_0_bits_3 =
s2_AFHOB_sel
? s2_AFHOB_src_afhob_0_bits_3
: s1_AFHOB_sel
? s1_AFHOB_src_afhob_0_bits_3
: s3_AFHOB_sel
? s3_AFHOB_src_afhob_0_bits_3
: redirect_AFHOB_sel
? redirect_AFHOB_src_afhob_0_bits_3
: stallAFHOB_src_afhob_0_bits_3;
endmodule

80
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_16(
input s2_BrNumOH_sel,
input [2:0] s2_BrNumOH_src,
input s1_BrNumOH_sel,
input [2:0] s1_BrNumOH_src,
input s3_BrNumOH_sel,
input [2:0] s3_BrNumOH_src,
input redirect_BrNumOH_sel,
input [2:0] redirect_BrNumOH_src,
input [2:0] stallBrNumOH_src,
output [2:0] out_res
);
assign out_res =
s2_BrNumOH_sel
? s2_BrNumOH_src
: s1_BrNumOH_sel
? s1_BrNumOH_src
: s3_BrNumOH_sel
? s3_BrNumOH_src
: redirect_BrNumOH_sel ? redirect_BrNumOH_src : stallBrNumOH_src;
endmodule

76
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_20(
input s2_new_bit_0_sel,
input s2_new_bit_0_src,
input s1_new_bit_0_sel,
input s1_new_bit_0_src,
input s3_new_bit_0_sel,
input s3_new_bit_0_src,
input redirect_new_bit_0_src,
output out_res
);
assign out_res =
s2_new_bit_0_sel
? s2_new_bit_0_src
: s1_new_bit_0_sel
? s1_new_bit_0_src
: s3_new_bit_0_sel ? s3_new_bit_0_src : redirect_new_bit_0_src;
endmodule

354
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_4(
input s2_FGH_sel,
input [10:0] s2_FGH_src_hist_17_folded_hist,
input [10:0] s2_FGH_src_hist_16_folded_hist,
input [6:0] s2_FGH_src_hist_15_folded_hist,
input [7:0] s2_FGH_src_hist_14_folded_hist,
input [8:0] s2_FGH_src_hist_13_folded_hist,
input [3:0] s2_FGH_src_hist_12_folded_hist,
input [7:0] s2_FGH_src_hist_11_folded_hist,
input [8:0] s2_FGH_src_hist_10_folded_hist,
input [6:0] s2_FGH_src_hist_9_folded_hist,
input [7:0] s2_FGH_src_hist_8_folded_hist,
input [6:0] s2_FGH_src_hist_7_folded_hist,
input [8:0] s2_FGH_src_hist_6_folded_hist,
input [6:0] s2_FGH_src_hist_5_folded_hist,
input [7:0] s2_FGH_src_hist_4_folded_hist,
input [7:0] s2_FGH_src_hist_3_folded_hist,
input [7:0] s2_FGH_src_hist_2_folded_hist,
input [10:0] s2_FGH_src_hist_1_folded_hist,
input [7:0] s2_FGH_src_hist_0_folded_hist,
input s1_FGH_sel,
input [10:0] s1_FGH_src_hist_17_folded_hist,
input [10:0] s1_FGH_src_hist_16_folded_hist,
input [6:0] s1_FGH_src_hist_15_folded_hist,
input [7:0] s1_FGH_src_hist_14_folded_hist,
input [8:0] s1_FGH_src_hist_13_folded_hist,
input [3:0] s1_FGH_src_hist_12_folded_hist,
input [7:0] s1_FGH_src_hist_11_folded_hist,
input [8:0] s1_FGH_src_hist_10_folded_hist,
input [6:0] s1_FGH_src_hist_9_folded_hist,
input [7:0] s1_FGH_src_hist_8_folded_hist,
input [6:0] s1_FGH_src_hist_7_folded_hist,
input [8:0] s1_FGH_src_hist_6_folded_hist,
input [6:0] s1_FGH_src_hist_5_folded_hist,
input [7:0] s1_FGH_src_hist_4_folded_hist,
input [7:0] s1_FGH_src_hist_3_folded_hist,
input [7:0] s1_FGH_src_hist_2_folded_hist,
input [10:0] s1_FGH_src_hist_1_folded_hist,
input [7:0] s1_FGH_src_hist_0_folded_hist,
input s3_FGH_sel,
input [10:0] s3_FGH_src_hist_17_folded_hist,
input [10:0] s3_FGH_src_hist_16_folded_hist,
input [6:0] s3_FGH_src_hist_15_folded_hist,
input [7:0] s3_FGH_src_hist_14_folded_hist,
input [8:0] s3_FGH_src_hist_13_folded_hist,
input [3:0] s3_FGH_src_hist_12_folded_hist,
input [7:0] s3_FGH_src_hist_11_folded_hist,
input [8:0] s3_FGH_src_hist_10_folded_hist,
input [6:0] s3_FGH_src_hist_9_folded_hist,
input [7:0] s3_FGH_src_hist_8_folded_hist,
input [6:0] s3_FGH_src_hist_7_folded_hist,
input [8:0] s3_FGH_src_hist_6_folded_hist,
input [6:0] s3_FGH_src_hist_5_folded_hist,
input [7:0] s3_FGH_src_hist_4_folded_hist,
input [7:0] s3_FGH_src_hist_3_folded_hist,
input [7:0] s3_FGH_src_hist_2_folded_hist,
input [10:0] s3_FGH_src_hist_1_folded_hist,
input [7:0] s3_FGH_src_hist_0_folded_hist,
input redirect_FGHT_sel,
input [10:0] redirect_FGHT_src_hist_17_folded_hist,
input [10:0] redirect_FGHT_src_hist_16_folded_hist,
input [6:0] redirect_FGHT_src_hist_15_folded_hist,
input [7:0] redirect_FGHT_src_hist_14_folded_hist,
input [8:0] redirect_FGHT_src_hist_13_folded_hist,
input [3:0] redirect_FGHT_src_hist_12_folded_hist,
input [7:0] redirect_FGHT_src_hist_11_folded_hist,
input [8:0] redirect_FGHT_src_hist_10_folded_hist,
input [6:0] redirect_FGHT_src_hist_9_folded_hist,
input [7:0] redirect_FGHT_src_hist_8_folded_hist,
input [6:0] redirect_FGHT_src_hist_7_folded_hist,
input [8:0] redirect_FGHT_src_hist_6_folded_hist,
input [6:0] redirect_FGHT_src_hist_5_folded_hist,
input [7:0] redirect_FGHT_src_hist_4_folded_hist,
input [7:0] redirect_FGHT_src_hist_3_folded_hist,
input [7:0] redirect_FGHT_src_hist_2_folded_hist,
input [10:0] redirect_FGHT_src_hist_1_folded_hist,
input [7:0] redirect_FGHT_src_hist_0_folded_hist,
input [10:0] stallFGH_src_hist_17_folded_hist,
input [10:0] stallFGH_src_hist_16_folded_hist,
input [6:0] stallFGH_src_hist_15_folded_hist,
input [7:0] stallFGH_src_hist_14_folded_hist,
input [8:0] stallFGH_src_hist_13_folded_hist,
input [3:0] stallFGH_src_hist_12_folded_hist,
input [7:0] stallFGH_src_hist_11_folded_hist,
input [8:0] stallFGH_src_hist_10_folded_hist,
input [6:0] stallFGH_src_hist_9_folded_hist,
input [7:0] stallFGH_src_hist_8_folded_hist,
input [6:0] stallFGH_src_hist_7_folded_hist,
input [8:0] stallFGH_src_hist_6_folded_hist,
input [6:0] stallFGH_src_hist_5_folded_hist,
input [7:0] stallFGH_src_hist_4_folded_hist,
input [7:0] stallFGH_src_hist_3_folded_hist,
input [7:0] stallFGH_src_hist_2_folded_hist,
input [10:0] stallFGH_src_hist_1_folded_hist,
input [7:0] stallFGH_src_hist_0_folded_hist,
output [10:0] out_res_hist_17_folded_hist,
output [10:0] out_res_hist_16_folded_hist,
output [6:0] out_res_hist_15_folded_hist,
output [7:0] out_res_hist_14_folded_hist,
output [8:0] out_res_hist_13_folded_hist,
output [3:0] out_res_hist_12_folded_hist,
output [7:0] out_res_hist_11_folded_hist,
output [8:0] out_res_hist_10_folded_hist,
output [6:0] out_res_hist_9_folded_hist,
output [7:0] out_res_hist_8_folded_hist,
output [6:0] out_res_hist_7_folded_hist,
output [8:0] out_res_hist_6_folded_hist,
output [6:0] out_res_hist_5_folded_hist,
output [7:0] out_res_hist_4_folded_hist,
output [7:0] out_res_hist_3_folded_hist,
output [7:0] out_res_hist_2_folded_hist,
output [10:0] out_res_hist_1_folded_hist,
output [7:0] out_res_hist_0_folded_hist
);
assign out_res_hist_17_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_17_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_17_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_17_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_17_folded_hist
: stallFGH_src_hist_17_folded_hist;
assign out_res_hist_16_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_16_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_16_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_16_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_16_folded_hist
: stallFGH_src_hist_16_folded_hist;
assign out_res_hist_15_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_15_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_15_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_15_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_15_folded_hist
: stallFGH_src_hist_15_folded_hist;
assign out_res_hist_14_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_14_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_14_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_14_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_14_folded_hist
: stallFGH_src_hist_14_folded_hist;
assign out_res_hist_13_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_13_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_13_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_13_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_13_folded_hist
: stallFGH_src_hist_13_folded_hist;
assign out_res_hist_12_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_12_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_12_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_12_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_12_folded_hist
: stallFGH_src_hist_12_folded_hist;
assign out_res_hist_11_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_11_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_11_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_11_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_11_folded_hist
: stallFGH_src_hist_11_folded_hist;
assign out_res_hist_10_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_10_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_10_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_10_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_10_folded_hist
: stallFGH_src_hist_10_folded_hist;
assign out_res_hist_9_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_9_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_9_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_9_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_9_folded_hist
: stallFGH_src_hist_9_folded_hist;
assign out_res_hist_8_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_8_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_8_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_8_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_8_folded_hist
: stallFGH_src_hist_8_folded_hist;
assign out_res_hist_7_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_7_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_7_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_7_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_7_folded_hist
: stallFGH_src_hist_7_folded_hist;
assign out_res_hist_6_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_6_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_6_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_6_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_6_folded_hist
: stallFGH_src_hist_6_folded_hist;
assign out_res_hist_5_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_5_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_5_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_5_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_5_folded_hist
: stallFGH_src_hist_5_folded_hist;
assign out_res_hist_4_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_4_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_4_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_4_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_4_folded_hist
: stallFGH_src_hist_4_folded_hist;
assign out_res_hist_3_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_3_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_3_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_3_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_3_folded_hist
: stallFGH_src_hist_3_folded_hist;
assign out_res_hist_2_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_2_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_2_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_2_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_2_folded_hist
: stallFGH_src_hist_2_folded_hist;
assign out_res_hist_1_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_1_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_1_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_1_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_1_folded_hist
: stallFGH_src_hist_1_folded_hist;
assign out_res_hist_0_folded_hist =
s2_FGH_sel
? s2_FGH_src_hist_0_folded_hist
: s1_FGH_sel
? s1_FGH_src_hist_0_folded_hist
: s3_FGH_sel
? s3_FGH_src_hist_0_folded_hist
: redirect_FGHT_sel
? redirect_FGHT_src_hist_0_folded_hist
: stallFGH_src_hist_0_folded_hist;
endmodule

94
rtl/BPUTop/PriorityMuxModule_8.sv Normal file
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@ -0,0 +1,94 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module PriorityMuxModule_8(
input s2_GHPtr_sel,
input s2_GHPtr_src_flag,
input [7:0] s2_GHPtr_src_value,
input s1_GHPtr_sel,
input s1_GHPtr_src_flag,
input [7:0] s1_GHPtr_src_value,
input s3_GHPtr_sel,
input s3_GHPtr_src_flag,
input [7:0] s3_GHPtr_src_value,
input redirect_GHPtr_sel,
input redirect_GHPtr_src_flag,
input [7:0] redirect_GHPtr_src_value,
input stallGHPtr_src_flag,
input [7:0] stallGHPtr_src_value,
output out_res_flag,
output [7:0] out_res_value
);
assign out_res_flag =
s2_GHPtr_sel
? s2_GHPtr_src_flag
: s1_GHPtr_sel
? s1_GHPtr_src_flag
: s3_GHPtr_sel
? s3_GHPtr_src_flag
: redirect_GHPtr_sel ? redirect_GHPtr_src_flag : stallGHPtr_src_flag;
assign out_res_value =
s2_GHPtr_sel
? s2_GHPtr_src_value
: s1_GHPtr_sel
? s1_GHPtr_src_value
: s3_GHPtr_sel
? s3_GHPtr_src_value
: redirect_GHPtr_sel ? redirect_GHPtr_src_value : stallGHPtr_src_value;
endmodule

883
rtl/BPUTop/RAS.sv Normal file
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@ -0,0 +1,883 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module RAS(
input clock,
input reset,
input [35:0] io_reset_vector,
input [40:0] io_in_bits_s0_pc_0,
input [40:0] io_in_bits_s0_pc_1,
input [40:0] io_in_bits_s0_pc_2,
input [40:0] io_in_bits_s0_pc_3,
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_0_hit,
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_1_hit,
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr,
input io_in_bits_resp_in_0_s2_full_pred_2_is_call,
input io_in_bits_resp_in_0_s2_full_pred_2_is_ret,
input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call,
input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_2_hit,
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0,
input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1,
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0,
input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0,
input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1,
input [40:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr,
input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr,
input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing,
input io_in_bits_resp_in_0_s2_full_pred_3_hit,
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_0_hit,
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_1_hit,
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr,
input io_in_bits_resp_in_0_s3_full_pred_2_is_call,
input io_in_bits_resp_in_0_s3_full_pred_2_is_ret,
input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_2_hit,
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0,
input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1,
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0,
input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target,
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0,
input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1,
input [40:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr,
input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr,
input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing,
input io_in_bits_resp_in_0_s3_full_pred_3_hit,
input io_in_bits_resp_in_0_last_stage_ftb_entry_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset,
input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower,
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat,
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing,
input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset,
input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower,
input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat,
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing,
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid,
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr,
input io_in_bits_resp_in_0_last_stage_ftb_entry_carry,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet,
input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr,
input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call,
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0,
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1,
output [40:0] io_out_s2_pc_0,
output [40:0] io_out_s2_pc_1,
output [40:0] io_out_s2_pc_2,
output [40:0] io_out_s2_pc_3,
output io_out_s2_full_pred_0_br_taken_mask_0,
output io_out_s2_full_pred_0_br_taken_mask_1,
output io_out_s2_full_pred_0_slot_valids_0,
output io_out_s2_full_pred_0_slot_valids_1,
output [40:0] io_out_s2_full_pred_0_targets_0,
output [40:0] io_out_s2_full_pred_0_targets_1,
output [3:0] io_out_s2_full_pred_0_offsets_0,
output [3:0] io_out_s2_full_pred_0_offsets_1,
output [40:0] io_out_s2_full_pred_0_fallThroughAddr,
output io_out_s2_full_pred_0_is_br_sharing,
output io_out_s2_full_pred_0_hit,
output io_out_s2_full_pred_1_br_taken_mask_0,
output io_out_s2_full_pred_1_br_taken_mask_1,
output io_out_s2_full_pred_1_slot_valids_0,
output io_out_s2_full_pred_1_slot_valids_1,
output [40:0] io_out_s2_full_pred_1_targets_0,
output [40:0] io_out_s2_full_pred_1_targets_1,
output [3:0] io_out_s2_full_pred_1_offsets_0,
output [3:0] io_out_s2_full_pred_1_offsets_1,
output [40:0] io_out_s2_full_pred_1_fallThroughAddr,
output io_out_s2_full_pred_1_is_br_sharing,
output io_out_s2_full_pred_1_hit,
output io_out_s2_full_pred_2_br_taken_mask_0,
output io_out_s2_full_pred_2_br_taken_mask_1,
output io_out_s2_full_pred_2_slot_valids_0,
output io_out_s2_full_pred_2_slot_valids_1,
output [40:0] io_out_s2_full_pred_2_targets_0,
output [40:0] io_out_s2_full_pred_2_targets_1,
output [3:0] io_out_s2_full_pred_2_offsets_0,
output [3:0] io_out_s2_full_pred_2_offsets_1,
output [40:0] io_out_s2_full_pred_2_fallThroughAddr,
output io_out_s2_full_pred_2_is_br_sharing,
output io_out_s2_full_pred_2_hit,
output io_out_s2_full_pred_3_br_taken_mask_0,
output io_out_s2_full_pred_3_br_taken_mask_1,
output io_out_s2_full_pred_3_slot_valids_0,
output io_out_s2_full_pred_3_slot_valids_1,
output [40:0] io_out_s2_full_pred_3_targets_0,
output [40:0] io_out_s2_full_pred_3_targets_1,
output [3:0] io_out_s2_full_pred_3_offsets_0,
output [3:0] io_out_s2_full_pred_3_offsets_1,
output [40:0] io_out_s2_full_pred_3_fallThroughAddr,
output io_out_s2_full_pred_3_fallThroughErr,
output io_out_s2_full_pred_3_is_br_sharing,
output io_out_s2_full_pred_3_hit,
output [40:0] io_out_s3_pc_0,
output [40:0] io_out_s3_pc_1,
output [40:0] io_out_s3_pc_2,
output [40:0] io_out_s3_pc_3,
output io_out_s3_full_pred_0_br_taken_mask_0,
output io_out_s3_full_pred_0_br_taken_mask_1,
output io_out_s3_full_pred_0_slot_valids_0,
output io_out_s3_full_pred_0_slot_valids_1,
output [40:0] io_out_s3_full_pred_0_targets_0,
output [40:0] io_out_s3_full_pred_0_targets_1,
output [40:0] io_out_s3_full_pred_0_fallThroughAddr,
output io_out_s3_full_pred_0_fallThroughErr,
output io_out_s3_full_pred_0_is_br_sharing,
output io_out_s3_full_pred_0_hit,
output io_out_s3_full_pred_1_br_taken_mask_0,
output io_out_s3_full_pred_1_br_taken_mask_1,
output io_out_s3_full_pred_1_slot_valids_0,
output io_out_s3_full_pred_1_slot_valids_1,
output [40:0] io_out_s3_full_pred_1_targets_0,
output [40:0] io_out_s3_full_pred_1_targets_1,
output [40:0] io_out_s3_full_pred_1_fallThroughAddr,
output io_out_s3_full_pred_1_fallThroughErr,
output io_out_s3_full_pred_1_is_br_sharing,
output io_out_s3_full_pred_1_hit,
output io_out_s3_full_pred_2_br_taken_mask_0,
output io_out_s3_full_pred_2_br_taken_mask_1,
output io_out_s3_full_pred_2_slot_valids_0,
output io_out_s3_full_pred_2_slot_valids_1,
output [40:0] io_out_s3_full_pred_2_targets_0,
output [40:0] io_out_s3_full_pred_2_targets_1,
output [40:0] io_out_s3_full_pred_2_fallThroughAddr,
output io_out_s3_full_pred_2_fallThroughErr,
output io_out_s3_full_pred_2_is_br_sharing,
output io_out_s3_full_pred_2_hit,
output io_out_s3_full_pred_3_br_taken_mask_0,
output io_out_s3_full_pred_3_br_taken_mask_1,
output io_out_s3_full_pred_3_slot_valids_0,
output io_out_s3_full_pred_3_slot_valids_1,
output [40:0] io_out_s3_full_pred_3_targets_0,
output [40:0] io_out_s3_full_pred_3_targets_1,
output [3:0] io_out_s3_full_pred_3_offsets_0,
output [3:0] io_out_s3_full_pred_3_offsets_1,
output [40:0] io_out_s3_full_pred_3_fallThroughAddr,
output io_out_s3_full_pred_3_fallThroughErr,
output io_out_s3_full_pred_3_is_br_sharing,
output io_out_s3_full_pred_3_hit,
output [222:0] io_out_last_stage_meta,
output [3:0] io_out_last_stage_spec_info_ssp,
output [1:0] io_out_last_stage_spec_info_sctr,
output io_out_last_stage_spec_info_TOSW_flag,
output [4:0] io_out_last_stage_spec_info_TOSW_value,
output io_out_last_stage_spec_info_TOSR_flag,
output [4:0] io_out_last_stage_spec_info_TOSR_value,
output io_out_last_stage_spec_info_NOS_flag,
output [4:0] io_out_last_stage_spec_info_NOS_value,
output [40:0] io_out_last_stage_spec_info_topAddr,
output io_out_last_stage_ftb_entry_valid,
output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset,
output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower,
output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat,
output io_out_last_stage_ftb_entry_brSlots_0_sharing,
output io_out_last_stage_ftb_entry_brSlots_0_valid,
output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset,
output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower,
output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat,
output io_out_last_stage_ftb_entry_tailSlot_sharing,
output io_out_last_stage_ftb_entry_tailSlot_valid,
output [3:0] io_out_last_stage_ftb_entry_pftAddr,
output io_out_last_stage_ftb_entry_carry,
output io_out_last_stage_ftb_entry_isCall,
output io_out_last_stage_ftb_entry_isRet,
output io_out_last_stage_ftb_entry_isJalr,
output io_out_last_stage_ftb_entry_last_may_be_rvi_call,
output io_out_last_stage_ftb_entry_always_taken_0,
output io_out_last_stage_ftb_entry_always_taken_1,
input io_ctrl_ras_enable,
input io_s0_fire_0,
input io_s0_fire_1,
input io_s0_fire_2,
input io_s0_fire_3,
input io_s1_fire_0,
input io_s1_fire_1,
input io_s1_fire_2,
input io_s1_fire_3,
input io_s2_fire_0,
input io_s2_fire_1,
input io_s2_fire_2,
input io_s2_fire_3,
input io_s3_fire_2,
input io_s3_redirect_2,
input io_update_valid,
input [3:0] io_update_bits_ftb_entry_tailSlot_offset,
input io_update_bits_ftb_entry_tailSlot_valid,
input io_update_bits_ftb_entry_isCall,
input io_update_bits_ftb_entry_isRet,
input io_update_bits_cfi_idx_valid,
input [3:0] io_update_bits_cfi_idx_bits,
input io_update_bits_jmp_taken,
input [222:0] io_update_bits_meta,
input io_redirect_valid,
input io_redirect_bits_level,
input [40:0] io_redirect_bits_cfiUpdate_pc,
input io_redirect_bits_cfiUpdate_pd_isRVC,
input io_redirect_bits_cfiUpdate_pd_isCall,
input io_redirect_bits_cfiUpdate_pd_isRet,
input [3:0] io_redirect_bits_cfiUpdate_ssp,
input [1:0] io_redirect_bits_cfiUpdate_sctr,
input io_redirect_bits_cfiUpdate_TOSW_flag,
input [4:0] io_redirect_bits_cfiUpdate_TOSW_value,
input io_redirect_bits_cfiUpdate_TOSR_flag,
input [4:0] io_redirect_bits_cfiUpdate_TOSR_value,
input io_redirect_bits_cfiUpdate_NOS_flag,
input [4:0] io_redirect_bits_cfiUpdate_NOS_value
);
wire [40:0] _RASStack_io_spec_pop_addr;
wire [3:0] _RASStack_io_ssp;
wire [2:0] _RASStack_io_sctr;
wire _RASStack_io_TOSR_flag;
wire [4:0] _RASStack_io_TOSR_value;
wire _RASStack_io_TOSW_flag;
wire [4:0] _RASStack_io_TOSW_value;
wire _RASStack_io_NOS_flag;
wire [4:0] _RASStack_io_NOS_value;
wire [35:0] _reset_vector_delay_io_out;
reg [40:0] s1_pc_dup_0;
reg [40:0] s1_pc_dup_1;
reg [40:0] s1_pc_dup_2;
reg [40:0] s1_pc_dup_3;
reg [40:0] s2_pc_dup_0;
reg [40:0] s2_pc_dup_1;
reg [40:0] s2_pc_dup_2;
reg [40:0] s2_pc_dup_3;
reg [40:0] s3_pc_dup_0;
reg [40:0] s3_pc_dup_1;
reg [40:0] s3_pc_dup_2;
reg [40:0] s3_pc_dup_3;
reg REG;
reg REG_1;
wire [40:0] _s2_spec_new_addr_T_1 =
41'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr
+ {39'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0});
wire _s2_spec_pop_T_8 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;
wire _s2_spec_pop_T_9 =
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;
wire s2_spec_push =
io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s2_full_pred_2_hit
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2;
wire s2_spec_pop =
io_s2_fire_2 & ~(_s2_spec_pop_T_8 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s2_full_pred_2_hit
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2;
wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable;
reg [40:0] s3_top;
reg [40:0] s3_spec_new_addr;
wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable;
reg s3_pushed_in_s2;
reg s3_popped_in_s2;
wire _s3_pop_T_8 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;
wire _s3_pop_T_9 =
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;
wire s3_push =
~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s3_full_pred_2_hit
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_is_call;
wire s3_pop =
~(_s3_pop_T_8 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
& io_in_bits_resp_in_0_s3_full_pred_2_hit
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
& io_in_bits_resp_in_0_s3_full_pred_2_is_ret;
reg [3:0] s3_meta_ssp;
reg [2:0] s3_meta_sctr;
reg s3_meta_TOSW_flag;
reg [4:0] s3_meta_TOSW_value;
reg s3_meta_TOSR_flag;
reg [4:0] s3_meta_TOSR_value;
reg s3_meta_NOS_flag;
reg [4:0] s3_meta_NOS_value;
reg redirect_next_valid_last_r;
reg redirect_next_bits_r_level;
reg [40:0] redirect_next_bits_r_cfiUpdate_pc;
reg redirect_next_bits_r_cfiUpdate_pd_isRVC;
reg redirect_next_bits_r_cfiUpdate_pd_isCall;
reg redirect_next_bits_r_cfiUpdate_pd_isRet;
reg [3:0] redirect_next_bits_r_cfiUpdate_ssp;
reg [1:0] redirect_next_bits_r_cfiUpdate_sctr;
reg redirect_next_bits_r_cfiUpdate_TOSW_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_TOSW_value;
reg redirect_next_bits_r_cfiUpdate_TOSR_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_TOSR_value;
reg redirect_next_bits_r_cfiUpdate_NOS_flag;
reg [4:0] redirect_next_bits_r_cfiUpdate_NOS_value;
wire _GEN_1 =
io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset;
wire [40:0] _GEN_2 = {5'h0, _reset_vector_delay_io_out};
always @(posedge clock) begin
if (REG_1) begin
s1_pc_dup_0 <= _GEN_2;
s1_pc_dup_1 <= _GEN_2;
s1_pc_dup_2 <= _GEN_2;
s1_pc_dup_3 <= _GEN_2;
end
else begin
if (io_s0_fire_0)
s1_pc_dup_0 <= io_in_bits_s0_pc_0;
if (io_s0_fire_1)
s1_pc_dup_1 <= io_in_bits_s0_pc_1;
if (io_s0_fire_2)
s1_pc_dup_2 <= io_in_bits_s0_pc_2;
if (io_s0_fire_3)
s1_pc_dup_3 <= io_in_bits_s0_pc_3;
end
if (io_s1_fire_0)
s2_pc_dup_0 <= s1_pc_dup_0;
if (io_s1_fire_1)
s2_pc_dup_1 <= s1_pc_dup_1;
if (io_s1_fire_2)
s2_pc_dup_2 <= s1_pc_dup_2;
if (io_s1_fire_3)
s2_pc_dup_3 <= s1_pc_dup_3;
if (io_s2_fire_0)
s3_pc_dup_0 <= s2_pc_dup_0;
if (io_s2_fire_1)
s3_pc_dup_1 <= s2_pc_dup_1;
if (io_s2_fire_2) begin
s3_pc_dup_2 <= s2_pc_dup_2;
s3_top <= _RASStack_io_spec_pop_addr;
s3_spec_new_addr <= _s2_spec_new_addr_T_1;
s3_pushed_in_s2 <= s2_spec_push;
s3_popped_in_s2 <= s2_spec_pop;
s3_meta_ssp <= _RASStack_io_ssp;
s3_meta_sctr <= _RASStack_io_sctr;
s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag;
s3_meta_TOSW_value <= _RASStack_io_TOSW_value;
s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag;
s3_meta_TOSR_value <= _RASStack_io_TOSR_value;
s3_meta_NOS_flag <= _RASStack_io_NOS_flag;
s3_meta_NOS_value <= _RASStack_io_NOS_value;
end
if (io_s2_fire_3)
s3_pc_dup_3 <= s2_pc_dup_3;
REG <= reset;
REG_1 <= REG & ~reset;
if (io_redirect_valid) begin
redirect_next_bits_r_level <= io_redirect_bits_level;
redirect_next_bits_r_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc;
redirect_next_bits_r_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC;
redirect_next_bits_r_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall;
redirect_next_bits_r_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet;
redirect_next_bits_r_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp;
redirect_next_bits_r_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr;
redirect_next_bits_r_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag;
redirect_next_bits_r_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value;
redirect_next_bits_r_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag;
redirect_next_bits_r_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value;
redirect_next_bits_r_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag;
redirect_next_bits_r_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
redirect_next_valid_last_r <= 1'h0;
else if (io_redirect_valid | redirect_next_valid_last_r)
redirect_next_valid_last_r <= io_redirect_valid;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:21];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin
_RANDOM[i] = `RANDOM;
end
s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][8:0]};
s1_pc_dup_1 = {_RANDOM[5'h1][31:9], _RANDOM[5'h2][17:0]};
s1_pc_dup_2 = {_RANDOM[5'h2][31:18], _RANDOM[5'h3][26:0]};
s1_pc_dup_3 = {_RANDOM[5'h3][31:27], _RANDOM[5'h4], _RANDOM[5'h5][3:0]};
s2_pc_dup_0 = {_RANDOM[5'h5][31:4], _RANDOM[5'h6][12:0]};
s2_pc_dup_1 = {_RANDOM[5'h6][31:13], _RANDOM[5'h7][21:0]};
s2_pc_dup_2 = {_RANDOM[5'h7][31:22], _RANDOM[5'h8][30:0]};
s2_pc_dup_3 = {_RANDOM[5'h8][31], _RANDOM[5'h9], _RANDOM[5'hA][7:0]};
s3_pc_dup_0 = {_RANDOM[5'hA][31:8], _RANDOM[5'hB][16:0]};
s3_pc_dup_1 = {_RANDOM[5'hB][31:17], _RANDOM[5'hC][25:0]};
s3_pc_dup_2 = {_RANDOM[5'hC][31:26], _RANDOM[5'hD], _RANDOM[5'hE][2:0]};
s3_pc_dup_3 = {_RANDOM[5'hE][31:3], _RANDOM[5'hF][11:0]};
REG = _RANDOM[5'hF][12];
REG_1 = _RANDOM[5'hF][13];
s3_top = {_RANDOM[5'hF][31:14], _RANDOM[5'h10][22:0]};
s3_spec_new_addr = {_RANDOM[5'h10][31:23], _RANDOM[5'h11]};
s3_pushed_in_s2 = _RANDOM[5'h12][0];
s3_popped_in_s2 = _RANDOM[5'h12][1];
s3_meta_ssp = _RANDOM[5'h12][5:2];
s3_meta_sctr = _RANDOM[5'h12][8:6];
s3_meta_TOSW_flag = _RANDOM[5'h12][9];
s3_meta_TOSW_value = _RANDOM[5'h12][14:10];
s3_meta_TOSR_flag = _RANDOM[5'h12][15];
s3_meta_TOSR_value = _RANDOM[5'h12][20:16];
s3_meta_NOS_flag = _RANDOM[5'h12][21];
s3_meta_NOS_value = _RANDOM[5'h12][26:22];
redirect_next_valid_last_r = _RANDOM[5'h12][27];
redirect_next_bits_r_level = _RANDOM[5'h13][17];
redirect_next_bits_r_cfiUpdate_pc = {_RANDOM[5'h13][31:19], _RANDOM[5'h14][27:0]};
redirect_next_bits_r_cfiUpdate_pd_isRVC = _RANDOM[5'h14][29];
redirect_next_bits_r_cfiUpdate_pd_isCall = _RANDOM[5'h15][0];
redirect_next_bits_r_cfiUpdate_pd_isRet = _RANDOM[5'h15][1];
redirect_next_bits_r_cfiUpdate_ssp = _RANDOM[5'h15][5:2];
redirect_next_bits_r_cfiUpdate_sctr = _RANDOM[5'h15][7:6];
redirect_next_bits_r_cfiUpdate_TOSW_flag = _RANDOM[5'h15][8];
redirect_next_bits_r_cfiUpdate_TOSW_value = _RANDOM[5'h15][13:9];
redirect_next_bits_r_cfiUpdate_TOSR_flag = _RANDOM[5'h15][14];
redirect_next_bits_r_cfiUpdate_TOSR_value = _RANDOM[5'h15][19:15];
redirect_next_bits_r_cfiUpdate_NOS_flag = _RANDOM[5'h15][20];
redirect_next_bits_r_cfiUpdate_NOS_value = _RANDOM[5'h15][25:21];
`endif // RANDOMIZE_REG_INIT
if (reset)
redirect_next_valid_last_r = 1'h0;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
DelayN_2 reset_vector_delay (
.clock (clock),
.io_in (io_reset_vector),
.io_out (_reset_vector_delay_io_out)
);
RASStack RASStack (
.clock (clock),
.reset (reset),
.io_spec_push_valid (s2_spec_push),
.io_spec_pop_valid (s2_spec_pop),
.io_spec_push_addr (_s2_spec_new_addr_T_1),
.io_s2_fire (io_s2_fire_2),
.io_s3_fire (io_s3_fire_2),
.io_s3_cancel
(io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)),
.io_s3_meta_ssp (s3_meta_ssp),
.io_s3_meta_sctr (s3_meta_sctr),
.io_s3_meta_TOSW_flag (s3_meta_TOSW_flag),
.io_s3_meta_TOSW_value (s3_meta_TOSW_value),
.io_s3_meta_TOSR_flag (s3_meta_TOSR_flag),
.io_s3_meta_TOSR_value (s3_meta_TOSR_value),
.io_s3_meta_NOS_flag (s3_meta_NOS_flag),
.io_s3_meta_NOS_value (s3_meta_NOS_value),
.io_s3_missed_pop (s3_pop & ~s3_popped_in_s2),
.io_s3_missed_push (s3_push & ~s3_pushed_in_s2),
.io_s3_pushAddr (s3_spec_new_addr),
.io_spec_pop_addr (_RASStack_io_spec_pop_addr),
.io_commit_push_valid
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
& io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken
& io_update_bits_cfi_idx_valid & _GEN_1),
.io_commit_pop_valid
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
& io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken
& io_update_bits_cfi_idx_valid & _GEN_1),
.io_commit_meta_TOSW_flag (io_update_bits_meta[17]),
.io_commit_meta_TOSW_value (io_update_bits_meta[16:12]),
.io_commit_meta_ssp (io_update_bits_meta[24:21]),
.io_redirect_valid (redirect_next_valid_last_r),
.io_redirect_isCall
(redirect_next_valid_last_r & ~redirect_next_bits_r_level
& redirect_next_bits_r_cfiUpdate_pd_isCall),
.io_redirect_isRet
(redirect_next_valid_last_r & ~redirect_next_bits_r_level
& redirect_next_bits_r_cfiUpdate_pd_isRet),
.io_redirect_meta_ssp (redirect_next_bits_r_cfiUpdate_ssp),
.io_redirect_meta_sctr ({1'h0, redirect_next_bits_r_cfiUpdate_sctr}),
.io_redirect_meta_TOSW_flag (redirect_next_bits_r_cfiUpdate_TOSW_flag),
.io_redirect_meta_TOSW_value (redirect_next_bits_r_cfiUpdate_TOSW_value),
.io_redirect_meta_TOSR_flag (redirect_next_bits_r_cfiUpdate_TOSR_flag),
.io_redirect_meta_TOSR_value (redirect_next_bits_r_cfiUpdate_TOSR_value),
.io_redirect_meta_NOS_flag (redirect_next_bits_r_cfiUpdate_NOS_flag),
.io_redirect_meta_NOS_value (redirect_next_bits_r_cfiUpdate_NOS_value),
.io_redirect_callAddr
(41'(redirect_next_bits_r_cfiUpdate_pc
+ {38'h0, redirect_next_bits_r_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})),
.io_ssp (_RASStack_io_ssp),
.io_sctr (_RASStack_io_sctr),
.io_TOSR_flag (_RASStack_io_TOSR_flag),
.io_TOSR_value (_RASStack_io_TOSR_value),
.io_TOSW_flag (_RASStack_io_TOSW_flag),
.io_TOSW_value (_RASStack_io_TOSW_value),
.io_NOS_flag (_RASStack_io_NOS_flag),
.io_NOS_value (_RASStack_io_NOS_value)
);
assign io_out_s2_pc_0 = s2_pc_dup_0;
assign io_out_s2_pc_1 = s2_pc_dup_1;
assign io_out_s2_pc_2 = s2_pc_dup_2;
assign io_out_s2_pc_3 = s2_pc_dup_3;
assign io_out_s2_full_pred_0_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0;
assign io_out_s2_full_pred_0_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1;
assign io_out_s2_full_pred_0_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0;
assign io_out_s2_full_pred_0_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1;
assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0;
assign io_out_s2_full_pred_0_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_0_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_0_targets_1;
assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0;
assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1;
assign io_out_s2_full_pred_0_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr;
assign io_out_s2_full_pred_0_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing;
assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit;
assign io_out_s2_full_pred_1_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0;
assign io_out_s2_full_pred_1_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1;
assign io_out_s2_full_pred_1_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0;
assign io_out_s2_full_pred_1_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1;
assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0;
assign io_out_s2_full_pred_1_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_1_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_1_targets_1;
assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0;
assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1;
assign io_out_s2_full_pred_1_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr;
assign io_out_s2_full_pred_1_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing;
assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit;
assign io_out_s2_full_pred_2_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0;
assign io_out_s2_full_pred_2_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1;
assign io_out_s2_full_pred_2_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0;
assign io_out_s2_full_pred_2_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1;
assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0;
assign io_out_s2_full_pred_2_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_2_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_2_targets_1;
assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0;
assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1;
assign io_out_s2_full_pred_2_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr;
assign io_out_s2_full_pred_2_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing;
assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit;
assign io_out_s2_full_pred_3_br_taken_mask_0 =
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0;
assign io_out_s2_full_pred_3_br_taken_mask_1 =
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1;
assign io_out_s2_full_pred_3_slot_valids_0 =
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0;
assign io_out_s2_full_pred_3_slot_valids_1 =
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1;
assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0;
assign io_out_s2_full_pred_3_targets_1 =
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
? (_GEN
? _RASStack_io_spec_pop_addr
: io_in_bits_resp_in_0_s2_full_pred_3_jalr_target)
: io_in_bits_resp_in_0_s2_full_pred_3_targets_1;
assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0;
assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1;
assign io_out_s2_full_pred_3_fallThroughAddr =
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr;
assign io_out_s2_full_pred_3_fallThroughErr =
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr;
assign io_out_s2_full_pred_3_is_br_sharing =
io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing;
assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit;
assign io_out_s3_pc_0 = s3_pc_dup_0;
assign io_out_s3_pc_1 = s3_pc_dup_1;
assign io_out_s3_pc_2 = s3_pc_dup_2;
assign io_out_s3_pc_3 = s3_pc_dup_3;
assign io_out_s3_full_pred_0_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0;
assign io_out_s3_full_pred_0_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1;
assign io_out_s3_full_pred_0_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0;
assign io_out_s3_full_pred_0_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1;
assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0;
assign io_out_s3_full_pred_0_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_0_targets_1;
assign io_out_s3_full_pred_0_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr;
assign io_out_s3_full_pred_0_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr;
assign io_out_s3_full_pred_0_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing;
assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit;
assign io_out_s3_full_pred_1_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0;
assign io_out_s3_full_pred_1_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1;
assign io_out_s3_full_pred_1_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0;
assign io_out_s3_full_pred_1_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1;
assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0;
assign io_out_s3_full_pred_1_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_1_targets_1;
assign io_out_s3_full_pred_1_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr;
assign io_out_s3_full_pred_1_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr;
assign io_out_s3_full_pred_1_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing;
assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit;
assign io_out_s3_full_pred_2_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0;
assign io_out_s3_full_pred_2_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1;
assign io_out_s3_full_pred_2_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0;
assign io_out_s3_full_pred_2_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1;
assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0;
assign io_out_s3_full_pred_2_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_2_targets_1;
assign io_out_s3_full_pred_2_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr;
assign io_out_s3_full_pred_2_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr;
assign io_out_s3_full_pred_2_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing;
assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit;
assign io_out_s3_full_pred_3_br_taken_mask_0 =
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0;
assign io_out_s3_full_pred_3_br_taken_mask_1 =
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1;
assign io_out_s3_full_pred_3_slot_valids_0 =
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0;
assign io_out_s3_full_pred_3_slot_valids_1 =
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1;
assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0;
assign io_out_s3_full_pred_3_targets_1 =
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target)
: io_in_bits_resp_in_0_s3_full_pred_3_targets_1;
assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0;
assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1;
assign io_out_s3_full_pred_3_fallThroughAddr =
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr;
assign io_out_s3_full_pred_3_fallThroughErr =
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr;
assign io_out_s3_full_pred_3_is_br_sharing =
io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing;
assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit;
assign io_out_last_stage_meta =
{198'h0,
s3_meta_ssp,
s3_meta_sctr,
s3_meta_TOSW_flag,
s3_meta_TOSW_value,
s3_meta_TOSR_flag,
s3_meta_TOSR_value,
s3_meta_NOS_flag,
s3_meta_NOS_value};
assign io_out_last_stage_spec_info_ssp = s3_meta_ssp;
assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0];
assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag;
assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value;
assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag;
assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value;
assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag;
assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value;
assign io_out_last_stage_spec_info_topAddr = s3_top;
assign io_out_last_stage_ftb_entry_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_valid;
assign io_out_last_stage_ftb_entry_brSlots_0_offset =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset;
assign io_out_last_stage_ftb_entry_brSlots_0_lower =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower;
assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat;
assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing;
assign io_out_last_stage_ftb_entry_brSlots_0_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid;
assign io_out_last_stage_ftb_entry_tailSlot_offset =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset;
assign io_out_last_stage_ftb_entry_tailSlot_lower =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower;
assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat;
assign io_out_last_stage_ftb_entry_tailSlot_sharing =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing;
assign io_out_last_stage_ftb_entry_tailSlot_valid =
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid;
assign io_out_last_stage_ftb_entry_pftAddr =
io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr;
assign io_out_last_stage_ftb_entry_carry =
io_in_bits_resp_in_0_last_stage_ftb_entry_carry;
assign io_out_last_stage_ftb_entry_isCall =
io_in_bits_resp_in_0_last_stage_ftb_entry_isCall;
assign io_out_last_stage_ftb_entry_isRet =
io_in_bits_resp_in_0_last_stage_ftb_entry_isRet;
assign io_out_last_stage_ftb_entry_isJalr =
io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr;
assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call;
assign io_out_last_stage_ftb_entry_always_taken_0 =
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0;
assign io_out_last_stage_ftb_entry_always_taken_1 =
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1;
endmodule

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rtl/BPUTop/RASStack.sv Normal file
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rtl/BPUTop/SCTable.sv Normal file
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@ -0,0 +1,244 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits_pc[8:1]),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (io_update_pc[8:1]),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (io_update_pc[8:1]),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (io_update_pc[8:1]),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

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rtl/BPUTop/SCTable_1.sv Normal file
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@ -0,0 +1,250 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_1(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [3:0] io_req_bits_folded_hist_hist_12_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [3:0] io_update_folded_hist_hist_12_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx =
{io_update_pc[8:5], io_update_pc[4:1] ^ io_update_folded_hist_hist_12_folded_hist};
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
({io_req_bits_pc[8:5],
io_req_bits_pc[4:1] ^ io_req_bits_folded_hist_hist_12_folded_hist}),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

248
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_2(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_11_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_11_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_11_folded_hist;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_11_folded_hist),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SCTable_3(
input clock,
input reset,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_2_folded_hist,
output [5:0] io_resp_ctrs_0_0,
output [5:0] io_resp_ctrs_0_1,
output [5:0] io_resp_ctrs_1_0,
output [5:0] io_resp_ctrs_1_1,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_2_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input [5:0] io_update_oldCtrs_0,
input [5:0] io_update_oldCtrs_1,
input io_update_tagePreds_0,
input io_update_tagePreds_1,
input io_update_takens_0,
input io_update_takens_1
);
wire _wrbypasses_1_io_hit;
wire _wrbypasses_1_io_hit_data_0_valid;
wire [5:0] _wrbypasses_1_io_hit_data_0_bits;
wire _wrbypasses_1_io_hit_data_1_valid;
wire [5:0] _wrbypasses_1_io_hit_data_1_bits;
wire _wrbypasses_0_io_hit;
wire _wrbypasses_0_io_hit_data_0_valid;
wire [5:0] _wrbypasses_0_io_hit_data_0_bits;
wire _wrbypasses_0_io_hit_data_1_valid;
wire [5:0] _wrbypasses_0_io_hit_data_1_bits;
wire [5:0] _table_io_r_resp_data_0;
wire [5:0] _table_io_r_resp_data_1;
wire [5:0] _table_io_r_resp_data_2;
wire [5:0] _table_io_r_resp_data_3;
reg [40:0] s1_pc;
wire updateWayMask_0 =
io_update_mask_0 & ~(io_update_pc[1]) & ~io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & ~io_update_tagePreds_1;
wire updateWayMask_1 =
io_update_mask_0 & ~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_mask_1
& io_update_pc[1] & io_update_tagePreds_1;
wire updateWayMask_2 =
io_update_mask_0 & io_update_pc[1] & ~io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & ~io_update_tagePreds_1;
wire updateWayMask_3 =
io_update_mask_0 & io_update_pc[1] & io_update_tagePreds_0 | io_update_mask_1
& ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [7:0] update_idx = io_update_pc[8:1] ^ io_update_folded_hist_hist_2_folded_hist;
wire ctrPos =
~(io_update_pc[1]) & io_update_tagePreds_0 | io_update_pc[1] & io_update_tagePreds_1;
wire [5:0] oldCtr =
(~(io_update_pc[1]) & _wrbypasses_0_io_hit | io_update_pc[1] & _wrbypasses_1_io_hit)
& (ctrPos
? ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_1_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_1_valid
: ~(io_update_pc[1]) & _wrbypasses_0_io_hit_data_0_valid | io_update_pc[1]
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos
? (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_1_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_1_bits : 6'h0)
: (io_update_pc[1] ? 6'h0 : _wrbypasses_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _wrbypasses_1_io_hit_data_0_bits : 6'h0))
: (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_0)
| (io_update_pc[1] ? io_update_oldCtrs_1 : 6'h0);
wire taken =
~(io_update_pc[1]) & io_update_takens_0 | io_update_pc[1] & io_update_takens_1;
wire [5:0] update_wdata_0 =
oldCtr == 6'h1F & taken
? 6'h1F
: oldCtr == 6'h20 & ~taken ? 6'h20 : taken ? 6'(oldCtr + 6'h1) : 6'(oldCtr - 6'h1);
wire ctrPos_1 =
io_update_pc[1] & io_update_tagePreds_0 | ~(io_update_pc[1]) & io_update_tagePreds_1;
wire [5:0] oldCtr_1 =
(io_update_pc[1] & _wrbypasses_0_io_hit | ~(io_update_pc[1]) & _wrbypasses_1_io_hit)
& (ctrPos_1
? io_update_pc[1] & _wrbypasses_0_io_hit_data_1_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_1_valid
: io_update_pc[1] & _wrbypasses_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _wrbypasses_1_io_hit_data_0_valid)
? (ctrPos_1
? (io_update_pc[1] ? _wrbypasses_0_io_hit_data_1_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_1_bits)
: (io_update_pc[1] ? _wrbypasses_0_io_hit_data_0_bits : 6'h0)
| (io_update_pc[1] ? 6'h0 : _wrbypasses_1_io_hit_data_0_bits))
: (io_update_pc[1] ? io_update_oldCtrs_0 : 6'h0)
| (io_update_pc[1] ? 6'h0 : io_update_oldCtrs_1);
wire taken_1 =
io_update_pc[1] & io_update_takens_0 | ~(io_update_pc[1]) & io_update_takens_1;
wire [5:0] update_wdata_1 =
oldCtr_1 == 6'h1F & taken_1
? 6'h1F
: oldCtr_1 == 6'h20 & ~taken_1
? 6'h20
: taken_1 ? 6'(oldCtr_1 + 6'h1) : 6'(oldCtr_1 - 6'h1);
wire [5:0] _GEN = io_update_pc[1] ? 6'h0 : update_wdata_0;
wire [5:0] _GEN_0 = io_update_pc[1] ? update_wdata_1 : 6'h0;
wire [5:0] _GEN_1 = io_update_pc[1] ? update_wdata_0 : 6'h0;
wire [5:0] _GEN_2 = io_update_pc[1] ? 6'h0 : update_wdata_1;
always @(posedge clock) begin
if (io_req_valid)
s1_pc <= io_req_bits_pc;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
s1_pc = {_RANDOM[1'h0][31:8], _RANDOM[1'h1][16:0]};
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_35 table_0 (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx
(io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_2_folded_hist),
.io_r_resp_data_0 (_table_io_r_resp_data_0),
.io_r_resp_data_1 (_table_io_r_resp_data_1),
.io_r_resp_data_2 (_table_io_r_resp_data_2),
.io_r_resp_data_3 (_table_io_r_resp_data_3),
.io_w_req_valid (io_update_mask_0 | io_update_mask_1),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0 (update_wdata_0),
.io_w_req_bits_data_1 (update_wdata_0),
.io_w_req_bits_data_2 (update_wdata_1),
.io_w_req_bits_data_3 (update_wdata_1),
.io_w_req_bits_waymask
({updateWayMask_3, updateWayMask_2, updateWayMask_1, updateWayMask_0})
);
WrBypass_33 wrbypasses_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN | _GEN_0),
.io_write_data_1 (_GEN | _GEN_0),
.io_write_way_mask_0
(~(io_update_pc[1]) & updateWayMask_0 | io_update_pc[1] & updateWayMask_2),
.io_write_way_mask_1
(~(io_update_pc[1]) & updateWayMask_1 | io_update_pc[1] & updateWayMask_3),
.io_hit (_wrbypasses_0_io_hit),
.io_hit_data_0_valid (_wrbypasses_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_0_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_0_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_0_io_hit_data_1_bits)
);
WrBypass_33 wrbypasses_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1),
.io_write_idx (update_idx),
.io_write_data_0 (_GEN_1 | _GEN_2),
.io_write_data_1 (_GEN_1 | _GEN_2),
.io_write_way_mask_0
(io_update_pc[1] & updateWayMask_0 | ~(io_update_pc[1]) & updateWayMask_2),
.io_write_way_mask_1
(io_update_pc[1] & updateWayMask_1 | ~(io_update_pc[1]) & updateWayMask_3),
.io_hit (_wrbypasses_1_io_hit),
.io_hit_data_0_valid (_wrbypasses_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypasses_1_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypasses_1_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypasses_1_io_hit_data_1_bits)
);
assign io_resp_ctrs_0_0 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_0)
| (s1_pc[1] ? _table_io_r_resp_data_2 : 6'h0);
assign io_resp_ctrs_0_1 =
(s1_pc[1] ? 6'h0 : _table_io_r_resp_data_1)
| (s1_pc[1] ? _table_io_r_resp_data_3 : 6'h0);
assign io_resp_ctrs_1_0 =
(s1_pc[1] ? _table_io_r_resp_data_0 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_2);
assign io_resp_ctrs_1_1 =
(s1_pc[1] ? _table_io_r_resp_data_1 : 6'h0)
| (s1_pc[1] ? 6'h0 : _table_io_r_resp_data_3);
endmodule

443
rtl/BPUTop/SRAMTemplate_13.sv Normal file
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@ -0,0 +1,443 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_13(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_entry_valid,
output [3:0] io_r_resp_data_0_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_0_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_0_entry_brSlots_0_tarStat,
output io_r_resp_data_0_entry_brSlots_0_sharing,
output io_r_resp_data_0_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_0_entry_tailSlot_offset,
output [19:0] io_r_resp_data_0_entry_tailSlot_lower,
output [1:0] io_r_resp_data_0_entry_tailSlot_tarStat,
output io_r_resp_data_0_entry_tailSlot_sharing,
output io_r_resp_data_0_entry_tailSlot_valid,
output [3:0] io_r_resp_data_0_entry_pftAddr,
output io_r_resp_data_0_entry_carry,
output io_r_resp_data_0_entry_isCall,
output io_r_resp_data_0_entry_isRet,
output io_r_resp_data_0_entry_isJalr,
output io_r_resp_data_0_entry_last_may_be_rvi_call,
output io_r_resp_data_0_entry_always_taken_0,
output io_r_resp_data_0_entry_always_taken_1,
output [19:0] io_r_resp_data_0_tag,
output io_r_resp_data_1_entry_valid,
output [3:0] io_r_resp_data_1_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_1_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_1_entry_brSlots_0_tarStat,
output io_r_resp_data_1_entry_brSlots_0_sharing,
output io_r_resp_data_1_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_1_entry_tailSlot_offset,
output [19:0] io_r_resp_data_1_entry_tailSlot_lower,
output [1:0] io_r_resp_data_1_entry_tailSlot_tarStat,
output io_r_resp_data_1_entry_tailSlot_sharing,
output io_r_resp_data_1_entry_tailSlot_valid,
output [3:0] io_r_resp_data_1_entry_pftAddr,
output io_r_resp_data_1_entry_carry,
output io_r_resp_data_1_entry_isCall,
output io_r_resp_data_1_entry_isRet,
output io_r_resp_data_1_entry_isJalr,
output io_r_resp_data_1_entry_last_may_be_rvi_call,
output io_r_resp_data_1_entry_always_taken_0,
output io_r_resp_data_1_entry_always_taken_1,
output [19:0] io_r_resp_data_1_tag,
output io_r_resp_data_2_entry_valid,
output [3:0] io_r_resp_data_2_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_2_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_2_entry_brSlots_0_tarStat,
output io_r_resp_data_2_entry_brSlots_0_sharing,
output io_r_resp_data_2_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_2_entry_tailSlot_offset,
output [19:0] io_r_resp_data_2_entry_tailSlot_lower,
output [1:0] io_r_resp_data_2_entry_tailSlot_tarStat,
output io_r_resp_data_2_entry_tailSlot_sharing,
output io_r_resp_data_2_entry_tailSlot_valid,
output [3:0] io_r_resp_data_2_entry_pftAddr,
output io_r_resp_data_2_entry_carry,
output io_r_resp_data_2_entry_isCall,
output io_r_resp_data_2_entry_isRet,
output io_r_resp_data_2_entry_isJalr,
output io_r_resp_data_2_entry_last_may_be_rvi_call,
output io_r_resp_data_2_entry_always_taken_0,
output io_r_resp_data_2_entry_always_taken_1,
output [19:0] io_r_resp_data_2_tag,
output io_r_resp_data_3_entry_valid,
output [3:0] io_r_resp_data_3_entry_brSlots_0_offset,
output [11:0] io_r_resp_data_3_entry_brSlots_0_lower,
output [1:0] io_r_resp_data_3_entry_brSlots_0_tarStat,
output io_r_resp_data_3_entry_brSlots_0_sharing,
output io_r_resp_data_3_entry_brSlots_0_valid,
output [3:0] io_r_resp_data_3_entry_tailSlot_offset,
output [19:0] io_r_resp_data_3_entry_tailSlot_lower,
output [1:0] io_r_resp_data_3_entry_tailSlot_tarStat,
output io_r_resp_data_3_entry_tailSlot_sharing,
output io_r_resp_data_3_entry_tailSlot_valid,
output [3:0] io_r_resp_data_3_entry_pftAddr,
output io_r_resp_data_3_entry_carry,
output io_r_resp_data_3_entry_isCall,
output io_r_resp_data_3_entry_isRet,
output io_r_resp_data_3_entry_isJalr,
output io_r_resp_data_3_entry_last_may_be_rvi_call,
output io_r_resp_data_3_entry_always_taken_0,
output io_r_resp_data_3_entry_always_taken_1,
output [19:0] io_r_resp_data_3_tag,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0_entry_valid,
input [3:0] io_w_req_bits_data_0_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_0_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_0_entry_brSlots_0_tarStat,
input io_w_req_bits_data_0_entry_brSlots_0_sharing,
input io_w_req_bits_data_0_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_0_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_0_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_0_entry_tailSlot_tarStat,
input io_w_req_bits_data_0_entry_tailSlot_sharing,
input io_w_req_bits_data_0_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_0_entry_pftAddr,
input io_w_req_bits_data_0_entry_carry,
input io_w_req_bits_data_0_entry_isCall,
input io_w_req_bits_data_0_entry_isRet,
input io_w_req_bits_data_0_entry_isJalr,
input io_w_req_bits_data_0_entry_last_may_be_rvi_call,
input io_w_req_bits_data_0_entry_always_taken_0,
input io_w_req_bits_data_0_entry_always_taken_1,
input [19:0] io_w_req_bits_data_0_tag,
input io_w_req_bits_data_1_entry_valid,
input [3:0] io_w_req_bits_data_1_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_1_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_1_entry_brSlots_0_tarStat,
input io_w_req_bits_data_1_entry_brSlots_0_sharing,
input io_w_req_bits_data_1_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_1_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_1_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_1_entry_tailSlot_tarStat,
input io_w_req_bits_data_1_entry_tailSlot_sharing,
input io_w_req_bits_data_1_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_1_entry_pftAddr,
input io_w_req_bits_data_1_entry_carry,
input io_w_req_bits_data_1_entry_isCall,
input io_w_req_bits_data_1_entry_isRet,
input io_w_req_bits_data_1_entry_isJalr,
input io_w_req_bits_data_1_entry_last_may_be_rvi_call,
input io_w_req_bits_data_1_entry_always_taken_0,
input io_w_req_bits_data_1_entry_always_taken_1,
input [19:0] io_w_req_bits_data_1_tag,
input io_w_req_bits_data_2_entry_valid,
input [3:0] io_w_req_bits_data_2_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_2_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_2_entry_brSlots_0_tarStat,
input io_w_req_bits_data_2_entry_brSlots_0_sharing,
input io_w_req_bits_data_2_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_2_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_2_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_2_entry_tailSlot_tarStat,
input io_w_req_bits_data_2_entry_tailSlot_sharing,
input io_w_req_bits_data_2_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_2_entry_pftAddr,
input io_w_req_bits_data_2_entry_carry,
input io_w_req_bits_data_2_entry_isCall,
input io_w_req_bits_data_2_entry_isRet,
input io_w_req_bits_data_2_entry_isJalr,
input io_w_req_bits_data_2_entry_last_may_be_rvi_call,
input io_w_req_bits_data_2_entry_always_taken_0,
input io_w_req_bits_data_2_entry_always_taken_1,
input [19:0] io_w_req_bits_data_2_tag,
input io_w_req_bits_data_3_entry_valid,
input [3:0] io_w_req_bits_data_3_entry_brSlots_0_offset,
input [11:0] io_w_req_bits_data_3_entry_brSlots_0_lower,
input [1:0] io_w_req_bits_data_3_entry_brSlots_0_tarStat,
input io_w_req_bits_data_3_entry_brSlots_0_sharing,
input io_w_req_bits_data_3_entry_brSlots_0_valid,
input [3:0] io_w_req_bits_data_3_entry_tailSlot_offset,
input [19:0] io_w_req_bits_data_3_entry_tailSlot_lower,
input [1:0] io_w_req_bits_data_3_entry_tailSlot_tarStat,
input io_w_req_bits_data_3_entry_tailSlot_sharing,
input io_w_req_bits_data_3_entry_tailSlot_valid,
input [3:0] io_w_req_bits_data_3_entry_pftAddr,
input io_w_req_bits_data_3_entry_carry,
input io_w_req_bits_data_3_entry_isCall,
input io_w_req_bits_data_3_entry_isRet,
input io_w_req_bits_data_3_entry_isJalr,
input io_w_req_bits_data_3_entry_last_may_be_rvi_call,
input io_w_req_bits_data_3_entry_always_taken_0,
input io_w_req_bits_data_3_entry_always_taken_1,
input [19:0] io_w_req_bits_data_3_tag,
input [3:0] io_w_req_bits_waymask
);
wire [8:0] setIdx;
wire realRen;
wire wen;
wire [319:0] _array_RW0_rdata;
reg _resetState;
reg [8:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 9'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 9'(_resetSet + 9'h1);
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
_resetState = _RANDOM[/*Zero width*/ 1'b0][0];
_resetSet = _RANDOM[/*Zero width*/ 1'b0][9:1];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 9'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_3 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState & io_w_req_bits_data_3_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_3_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_3_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_3_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_3_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_3_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_3_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_3_entry_pftAddr,
~_resetState & io_w_req_bits_data_3_entry_carry,
~_resetState & io_w_req_bits_data_3_entry_isCall,
~_resetState & io_w_req_bits_data_3_entry_isRet,
~_resetState & io_w_req_bits_data_3_entry_isJalr,
~_resetState & io_w_req_bits_data_3_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_3_entry_always_taken_1,
~_resetState & io_w_req_bits_data_3_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_3_tag,
~_resetState & io_w_req_bits_data_2_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_2_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_2_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_2_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_2_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_2_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_2_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_2_entry_pftAddr,
~_resetState & io_w_req_bits_data_2_entry_carry,
~_resetState & io_w_req_bits_data_2_entry_isCall,
~_resetState & io_w_req_bits_data_2_entry_isRet,
~_resetState & io_w_req_bits_data_2_entry_isJalr,
~_resetState & io_w_req_bits_data_2_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_2_entry_always_taken_1,
~_resetState & io_w_req_bits_data_2_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_2_tag,
~_resetState & io_w_req_bits_data_1_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_1_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_1_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_1_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_1_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_1_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_1_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_1_entry_pftAddr,
~_resetState & io_w_req_bits_data_1_entry_carry,
~_resetState & io_w_req_bits_data_1_entry_isCall,
~_resetState & io_w_req_bits_data_1_entry_isRet,
~_resetState & io_w_req_bits_data_1_entry_isJalr,
~_resetState & io_w_req_bits_data_1_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_1_entry_always_taken_1,
~_resetState & io_w_req_bits_data_1_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_1_tag,
~_resetState & io_w_req_bits_data_0_entry_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_brSlots_0_offset,
_resetState ? 12'h0 : io_w_req_bits_data_0_entry_brSlots_0_lower,
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_brSlots_0_tarStat,
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_sharing,
~_resetState & io_w_req_bits_data_0_entry_brSlots_0_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_tailSlot_offset,
_resetState ? 20'h0 : io_w_req_bits_data_0_entry_tailSlot_lower,
_resetState ? 2'h0 : io_w_req_bits_data_0_entry_tailSlot_tarStat,
~_resetState & io_w_req_bits_data_0_entry_tailSlot_sharing,
~_resetState & io_w_req_bits_data_0_entry_tailSlot_valid,
_resetState ? 4'h0 : io_w_req_bits_data_0_entry_pftAddr,
~_resetState & io_w_req_bits_data_0_entry_carry,
~_resetState & io_w_req_bits_data_0_entry_isCall,
~_resetState & io_w_req_bits_data_0_entry_isRet,
~_resetState & io_w_req_bits_data_0_entry_isJalr,
~_resetState & io_w_req_bits_data_0_entry_last_may_be_rvi_call,
~_resetState & io_w_req_bits_data_0_entry_always_taken_1,
~_resetState & io_w_req_bits_data_0_entry_always_taken_0,
_resetState ? 20'h0 : io_w_req_bits_data_0_tag}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 4'hF : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0_entry_valid = _array_RW0_rdata[79];
assign io_r_resp_data_0_entry_brSlots_0_offset = _array_RW0_rdata[78:75];
assign io_r_resp_data_0_entry_brSlots_0_lower = _array_RW0_rdata[74:63];
assign io_r_resp_data_0_entry_brSlots_0_tarStat = _array_RW0_rdata[62:61];
assign io_r_resp_data_0_entry_brSlots_0_sharing = _array_RW0_rdata[60];
assign io_r_resp_data_0_entry_brSlots_0_valid = _array_RW0_rdata[59];
assign io_r_resp_data_0_entry_tailSlot_offset = _array_RW0_rdata[58:55];
assign io_r_resp_data_0_entry_tailSlot_lower = _array_RW0_rdata[54:35];
assign io_r_resp_data_0_entry_tailSlot_tarStat = _array_RW0_rdata[34:33];
assign io_r_resp_data_0_entry_tailSlot_sharing = _array_RW0_rdata[32];
assign io_r_resp_data_0_entry_tailSlot_valid = _array_RW0_rdata[31];
assign io_r_resp_data_0_entry_pftAddr = _array_RW0_rdata[30:27];
assign io_r_resp_data_0_entry_carry = _array_RW0_rdata[26];
assign io_r_resp_data_0_entry_isCall = _array_RW0_rdata[25];
assign io_r_resp_data_0_entry_isRet = _array_RW0_rdata[24];
assign io_r_resp_data_0_entry_isJalr = _array_RW0_rdata[23];
assign io_r_resp_data_0_entry_last_may_be_rvi_call = _array_RW0_rdata[22];
assign io_r_resp_data_0_entry_always_taken_0 = _array_RW0_rdata[20];
assign io_r_resp_data_0_entry_always_taken_1 = _array_RW0_rdata[21];
assign io_r_resp_data_0_tag = _array_RW0_rdata[19:0];
assign io_r_resp_data_1_entry_valid = _array_RW0_rdata[159];
assign io_r_resp_data_1_entry_brSlots_0_offset = _array_RW0_rdata[158:155];
assign io_r_resp_data_1_entry_brSlots_0_lower = _array_RW0_rdata[154:143];
assign io_r_resp_data_1_entry_brSlots_0_tarStat = _array_RW0_rdata[142:141];
assign io_r_resp_data_1_entry_brSlots_0_sharing = _array_RW0_rdata[140];
assign io_r_resp_data_1_entry_brSlots_0_valid = _array_RW0_rdata[139];
assign io_r_resp_data_1_entry_tailSlot_offset = _array_RW0_rdata[138:135];
assign io_r_resp_data_1_entry_tailSlot_lower = _array_RW0_rdata[134:115];
assign io_r_resp_data_1_entry_tailSlot_tarStat = _array_RW0_rdata[114:113];
assign io_r_resp_data_1_entry_tailSlot_sharing = _array_RW0_rdata[112];
assign io_r_resp_data_1_entry_tailSlot_valid = _array_RW0_rdata[111];
assign io_r_resp_data_1_entry_pftAddr = _array_RW0_rdata[110:107];
assign io_r_resp_data_1_entry_carry = _array_RW0_rdata[106];
assign io_r_resp_data_1_entry_isCall = _array_RW0_rdata[105];
assign io_r_resp_data_1_entry_isRet = _array_RW0_rdata[104];
assign io_r_resp_data_1_entry_isJalr = _array_RW0_rdata[103];
assign io_r_resp_data_1_entry_last_may_be_rvi_call = _array_RW0_rdata[102];
assign io_r_resp_data_1_entry_always_taken_0 = _array_RW0_rdata[100];
assign io_r_resp_data_1_entry_always_taken_1 = _array_RW0_rdata[101];
assign io_r_resp_data_1_tag = _array_RW0_rdata[99:80];
assign io_r_resp_data_2_entry_valid = _array_RW0_rdata[239];
assign io_r_resp_data_2_entry_brSlots_0_offset = _array_RW0_rdata[238:235];
assign io_r_resp_data_2_entry_brSlots_0_lower = _array_RW0_rdata[234:223];
assign io_r_resp_data_2_entry_brSlots_0_tarStat = _array_RW0_rdata[222:221];
assign io_r_resp_data_2_entry_brSlots_0_sharing = _array_RW0_rdata[220];
assign io_r_resp_data_2_entry_brSlots_0_valid = _array_RW0_rdata[219];
assign io_r_resp_data_2_entry_tailSlot_offset = _array_RW0_rdata[218:215];
assign io_r_resp_data_2_entry_tailSlot_lower = _array_RW0_rdata[214:195];
assign io_r_resp_data_2_entry_tailSlot_tarStat = _array_RW0_rdata[194:193];
assign io_r_resp_data_2_entry_tailSlot_sharing = _array_RW0_rdata[192];
assign io_r_resp_data_2_entry_tailSlot_valid = _array_RW0_rdata[191];
assign io_r_resp_data_2_entry_pftAddr = _array_RW0_rdata[190:187];
assign io_r_resp_data_2_entry_carry = _array_RW0_rdata[186];
assign io_r_resp_data_2_entry_isCall = _array_RW0_rdata[185];
assign io_r_resp_data_2_entry_isRet = _array_RW0_rdata[184];
assign io_r_resp_data_2_entry_isJalr = _array_RW0_rdata[183];
assign io_r_resp_data_2_entry_last_may_be_rvi_call = _array_RW0_rdata[182];
assign io_r_resp_data_2_entry_always_taken_0 = _array_RW0_rdata[180];
assign io_r_resp_data_2_entry_always_taken_1 = _array_RW0_rdata[181];
assign io_r_resp_data_2_tag = _array_RW0_rdata[179:160];
assign io_r_resp_data_3_entry_valid = _array_RW0_rdata[319];
assign io_r_resp_data_3_entry_brSlots_0_offset = _array_RW0_rdata[318:315];
assign io_r_resp_data_3_entry_brSlots_0_lower = _array_RW0_rdata[314:303];
assign io_r_resp_data_3_entry_brSlots_0_tarStat = _array_RW0_rdata[302:301];
assign io_r_resp_data_3_entry_brSlots_0_sharing = _array_RW0_rdata[300];
assign io_r_resp_data_3_entry_brSlots_0_valid = _array_RW0_rdata[299];
assign io_r_resp_data_3_entry_tailSlot_offset = _array_RW0_rdata[298:295];
assign io_r_resp_data_3_entry_tailSlot_lower = _array_RW0_rdata[294:275];
assign io_r_resp_data_3_entry_tailSlot_tarStat = _array_RW0_rdata[274:273];
assign io_r_resp_data_3_entry_tailSlot_sharing = _array_RW0_rdata[272];
assign io_r_resp_data_3_entry_tailSlot_valid = _array_RW0_rdata[271];
assign io_r_resp_data_3_entry_pftAddr = _array_RW0_rdata[270:267];
assign io_r_resp_data_3_entry_carry = _array_RW0_rdata[266];
assign io_r_resp_data_3_entry_isCall = _array_RW0_rdata[265];
assign io_r_resp_data_3_entry_isRet = _array_RW0_rdata[264];
assign io_r_resp_data_3_entry_isJalr = _array_RW0_rdata[263];
assign io_r_resp_data_3_entry_last_may_be_rvi_call = _array_RW0_rdata[262];
assign io_r_resp_data_3_entry_always_taken_0 = _array_RW0_rdata[260];
assign io_r_resp_data_3_entry_always_taken_1 = _array_RW0_rdata[261];
assign io_r_resp_data_3_tag = _array_RW0_rdata[259:240];
endmodule

248
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_14(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output io_r_resp_data_0,
output io_r_resp_data_1,
output io_r_resp_data_2,
output io_r_resp_data_3,
output io_r_resp_data_4,
output io_r_resp_data_5,
output io_r_resp_data_6,
output io_r_resp_data_7,
output io_r_resp_data_8,
output io_r_resp_data_9,
output io_r_resp_data_10,
output io_r_resp_data_11,
output io_r_resp_data_12,
output io_r_resp_data_13,
output io_r_resp_data_14,
output io_r_resp_data_15,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input io_w_req_bits_data_0,
input io_w_req_bits_data_1,
input io_w_req_bits_data_2,
input io_w_req_bits_data_3,
input io_w_req_bits_data_4,
input io_w_req_bits_data_5,
input io_w_req_bits_data_6,
input io_w_req_bits_data_7,
input io_w_req_bits_data_8,
input io_w_req_bits_data_9,
input io_w_req_bits_data_10,
input io_w_req_bits_data_11,
input io_w_req_bits_data_12,
input io_w_req_bits_data_13,
input io_w_req_bits_data_14,
input io_w_req_bits_data_15,
input [15:0] io_w_req_bits_waymask,
input extra_reset
);
wire [7:0] setIdx;
wire realRen;
wire wen;
wire [15:0] _array_RW0_rdata;
reg _resetState;
reg [7:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg rdata_hold_data_0;
reg rdata_hold_data_1;
reg rdata_hold_data_2;
reg rdata_hold_data_3;
reg rdata_hold_data_4;
reg rdata_hold_data_5;
reg rdata_hold_data_6;
reg rdata_hold_data_7;
reg rdata_hold_data_8;
reg rdata_hold_data_9;
reg rdata_hold_data_10;
reg rdata_hold_data_11;
reg rdata_hold_data_12;
reg rdata_hold_data_13;
reg rdata_hold_data_14;
reg rdata_hold_data_15;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 8'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= extra_reset | ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 8'(_resetSet + 8'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[0];
rdata_hold_data_1 <= _array_RW0_rdata[1];
rdata_hold_data_2 <= _array_RW0_rdata[2];
rdata_hold_data_3 <= _array_RW0_rdata[3];
rdata_hold_data_4 <= _array_RW0_rdata[4];
rdata_hold_data_5 <= _array_RW0_rdata[5];
rdata_hold_data_6 <= _array_RW0_rdata[6];
rdata_hold_data_7 <= _array_RW0_rdata[7];
rdata_hold_data_8 <= _array_RW0_rdata[8];
rdata_hold_data_9 <= _array_RW0_rdata[9];
rdata_hold_data_10 <= _array_RW0_rdata[10];
rdata_hold_data_11 <= _array_RW0_rdata[11];
rdata_hold_data_12 <= _array_RW0_rdata[12];
rdata_hold_data_13 <= _array_RW0_rdata[13];
rdata_hold_data_14 <= _array_RW0_rdata[14];
rdata_hold_data_15 <= _array_RW0_rdata[15];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:33];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[6'h0][0];
_resetSet = _RANDOM[6'h0][8:1];
rdata_last_r = _RANDOM[6'h21][10];
rdata_hold_data_0 = _RANDOM[6'h21][11];
rdata_hold_data_1 = _RANDOM[6'h21][12];
rdata_hold_data_2 = _RANDOM[6'h21][13];
rdata_hold_data_3 = _RANDOM[6'h21][14];
rdata_hold_data_4 = _RANDOM[6'h21][15];
rdata_hold_data_5 = _RANDOM[6'h21][16];
rdata_hold_data_6 = _RANDOM[6'h21][17];
rdata_hold_data_7 = _RANDOM[6'h21][18];
rdata_hold_data_8 = _RANDOM[6'h21][19];
rdata_hold_data_9 = _RANDOM[6'h21][20];
rdata_hold_data_10 = _RANDOM[6'h21][21];
rdata_hold_data_11 = _RANDOM[6'h21][22];
rdata_hold_data_12 = _RANDOM[6'h21][23];
rdata_hold_data_13 = _RANDOM[6'h21][24];
rdata_hold_data_14 = _RANDOM[6'h21][25];
rdata_hold_data_15 = _RANDOM[6'h21][26];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 8'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_4 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState & io_w_req_bits_data_15,
~_resetState & io_w_req_bits_data_14,
~_resetState & io_w_req_bits_data_13,
~_resetState & io_w_req_bits_data_12,
~_resetState & io_w_req_bits_data_11,
~_resetState & io_w_req_bits_data_10,
~_resetState & io_w_req_bits_data_9,
~_resetState & io_w_req_bits_data_8,
~_resetState & io_w_req_bits_data_7,
~_resetState & io_w_req_bits_data_6,
~_resetState & io_w_req_bits_data_5,
~_resetState & io_w_req_bits_data_4,
~_resetState & io_w_req_bits_data_3,
~_resetState & io_w_req_bits_data_2,
~_resetState & io_w_req_bits_data_1,
~_resetState & io_w_req_bits_data_0}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 16'hFFFF : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0 = rdata_last_r ? _array_RW0_rdata[0] : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? _array_RW0_rdata[1] : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? _array_RW0_rdata[2] : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? _array_RW0_rdata[3] : rdata_hold_data_3;
assign io_r_resp_data_4 = rdata_last_r ? _array_RW0_rdata[4] : rdata_hold_data_4;
assign io_r_resp_data_5 = rdata_last_r ? _array_RW0_rdata[5] : rdata_hold_data_5;
assign io_r_resp_data_6 = rdata_last_r ? _array_RW0_rdata[6] : rdata_hold_data_6;
assign io_r_resp_data_7 = rdata_last_r ? _array_RW0_rdata[7] : rdata_hold_data_7;
assign io_r_resp_data_8 = rdata_last_r ? _array_RW0_rdata[8] : rdata_hold_data_8;
assign io_r_resp_data_9 = rdata_last_r ? _array_RW0_rdata[9] : rdata_hold_data_9;
assign io_r_resp_data_10 = rdata_last_r ? _array_RW0_rdata[10] : rdata_hold_data_10;
assign io_r_resp_data_11 = rdata_last_r ? _array_RW0_rdata[11] : rdata_hold_data_11;
assign io_r_resp_data_12 = rdata_last_r ? _array_RW0_rdata[12] : rdata_hold_data_12;
assign io_r_resp_data_13 = rdata_last_r ? _array_RW0_rdata[13] : rdata_hold_data_13;
assign io_r_resp_data_14 = rdata_last_r ? _array_RW0_rdata[14] : rdata_hold_data_14;
assign io_r_resp_data_15 = rdata_last_r ? _array_RW0_rdata[15] : rdata_hold_data_15;
endmodule

165
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_15(
input clock,
input reset,
output io_r_req_ready,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [7:0] io_r_resp_data_0_tag,
output [2:0] io_r_resp_data_0_ctr,
output io_r_resp_data_1_valid,
output [7:0] io_r_resp_data_1_tag,
output [2:0] io_r_resp_data_1_ctr,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [7:0] io_w_req_bits_data_0_tag,
input [2:0] io_w_req_bits_data_0_ctr,
input [7:0] io_w_req_bits_data_1_tag,
input [2:0] io_w_req_bits_data_1_ctr,
input [1:0] io_w_req_bits_waymask
);
wire [8:0] setIdx;
wire realRen;
wire wen;
wire [23:0] _array_RW0_rdata;
reg _resetState;
reg [8:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [11:0] rdata_hold_data_0;
reg [11:0] rdata_hold_data_1;
wire [11:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[11:0] : rdata_hold_data_0;
wire [11:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[23:12] : rdata_hold_data_1;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 9'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 9'(_resetSet + 9'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[11:0];
rdata_hold_data_1 <= _array_RW0_rdata[23:12];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:5];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[3'h0][0];
_resetSet = _RANDOM[3'h0][9:1];
rdata_last_r = _RANDOM[3'h4][31];
rdata_hold_data_0 = _RANDOM[3'h5][11:0];
rdata_hold_data_1 = _RANDOM[3'h5][23:12];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 9'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_5 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 8'h0 : io_w_req_bits_data_1_tag,
_resetState ? 3'h0 : io_w_req_bits_data_1_ctr,
~_resetState,
_resetState ? 8'h0 : io_w_req_bits_data_0_tag,
_resetState ? 3'h0 : io_w_req_bits_data_0_ctr}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)
);
assign io_r_req_ready = ~_resetState & ~wen;
assign io_r_resp_data_0_valid = _rdata_T_0[11];
assign io_r_resp_data_0_tag = _rdata_T_0[10:3];
assign io_r_resp_data_0_ctr = _rdata_T_0[2:0];
assign io_r_resp_data_1_valid = _rdata_T_1[11];
assign io_r_resp_data_1_tag = _rdata_T_1[10:3];
assign io_r_resp_data_1_ctr = _rdata_T_1[2:0];
endmodule

229
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_34(
input clock,
input reset,
input io_r_req_valid,
input [8:0] io_r_req_bits_setIdx,
output [1:0] io_r_resp_data_0,
output [1:0] io_r_resp_data_1,
output [1:0] io_r_resp_data_2,
output [1:0] io_r_resp_data_3,
output [1:0] io_r_resp_data_4,
output [1:0] io_r_resp_data_5,
output [1:0] io_r_resp_data_6,
output [1:0] io_r_resp_data_7,
input io_w_req_valid,
input [8:0] io_w_req_bits_setIdx,
input [1:0] io_w_req_bits_data_0,
input [1:0] io_w_req_bits_data_1,
input [1:0] io_w_req_bits_data_2,
input [1:0] io_w_req_bits_data_3,
input [1:0] io_w_req_bits_data_4,
input [1:0] io_w_req_bits_data_5,
input [1:0] io_w_req_bits_data_6,
input [1:0] io_w_req_bits_data_7,
input [7:0] io_w_req_bits_waymask
);
wire [15:0] _array_R0_data;
reg [1:0] bypass_wdata_r_0;
reg [1:0] bypass_wdata_r_1;
reg [1:0] bypass_wdata_r_2;
reg [1:0] bypass_wdata_r_3;
reg [1:0] bypass_wdata_r_4;
reg [1:0] bypass_wdata_r_5;
reg [1:0] bypass_wdata_r_6;
reg [1:0] bypass_wdata_r_7;
wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid;
reg bypass_mask_need_check_reg_last_r;
reg [8:0] bypass_mask_waddr_reg;
reg [8:0] bypass_mask_raddr_reg;
reg [7:0] bypass_mask_wmask_reg;
wire [7:0] bypass_mask =
{8{bypass_mask_need_check_reg_last_r
& bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg;
wire [1:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[1:0];
wire [1:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[3:2];
wire [1:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[5:4];
wire [1:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[7:6];
wire [1:0] mem_rdata_4 = bypass_mask[4] ? bypass_wdata_r_4 : _array_R0_data[9:8];
wire [1:0] mem_rdata_5 = bypass_mask[5] ? bypass_wdata_r_5 : _array_R0_data[11:10];
wire [1:0] mem_rdata_6 = bypass_mask[6] ? bypass_wdata_r_6 : _array_R0_data[13:12];
wire [1:0] mem_rdata_7 = bypass_mask[7] ? bypass_wdata_r_7 : _array_R0_data[15:14];
reg rdata_last_r;
reg [1:0] rdata_hold_data_0;
reg [1:0] rdata_hold_data_1;
reg [1:0] rdata_hold_data_2;
reg [1:0] rdata_hold_data_3;
reg [1:0] rdata_hold_data_4;
reg [1:0] rdata_hold_data_5;
reg [1:0] rdata_hold_data_6;
reg [1:0] rdata_hold_data_7;
always @(posedge clock) begin
if (io_w_req_valid & io_r_req_valid) begin
bypass_wdata_r_0 <= io_w_req_bits_data_0;
bypass_wdata_r_1 <= io_w_req_bits_data_1;
bypass_wdata_r_2 <= io_w_req_bits_data_2;
bypass_wdata_r_3 <= io_w_req_bits_data_3;
bypass_wdata_r_4 <= io_w_req_bits_data_4;
bypass_wdata_r_5 <= io_w_req_bits_data_5;
bypass_wdata_r_6 <= io_w_req_bits_data_6;
bypass_wdata_r_7 <= io_w_req_bits_data_7;
end
if (bypass_mask_need_check) begin
bypass_mask_waddr_reg <= io_w_req_bits_setIdx;
bypass_mask_raddr_reg <= io_r_req_bits_setIdx;
bypass_mask_wmask_reg <= io_w_req_bits_waymask;
end
if (rdata_last_r) begin
rdata_hold_data_0 <= mem_rdata_0;
rdata_hold_data_1 <= mem_rdata_1;
rdata_hold_data_2 <= mem_rdata_2;
rdata_hold_data_3 <= mem_rdata_3;
rdata_hold_data_4 <= mem_rdata_4;
rdata_hold_data_5 <= mem_rdata_5;
rdata_hold_data_6 <= mem_rdata_6;
rdata_hold_data_7 <= mem_rdata_7;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset) begin
bypass_mask_need_check_reg_last_r <= 1'h0;
rdata_last_r <= 1'h0;
end
else begin
if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)
bypass_mask_need_check_reg_last_r <= bypass_mask_need_check;
if (io_r_req_valid | rdata_last_r)
rdata_last_r <= io_r_req_valid;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
bypass_wdata_r_0 = _RANDOM[1'h0][1:0];
bypass_wdata_r_1 = _RANDOM[1'h0][3:2];
bypass_wdata_r_2 = _RANDOM[1'h0][5:4];
bypass_wdata_r_3 = _RANDOM[1'h0][7:6];
bypass_wdata_r_4 = _RANDOM[1'h0][9:8];
bypass_wdata_r_5 = _RANDOM[1'h0][11:10];
bypass_wdata_r_6 = _RANDOM[1'h0][13:12];
bypass_wdata_r_7 = _RANDOM[1'h0][15:14];
bypass_mask_need_check_reg_last_r = _RANDOM[1'h0][16];
bypass_mask_waddr_reg = _RANDOM[1'h0][25:17];
bypass_mask_raddr_reg = {_RANDOM[1'h0][31:26], _RANDOM[1'h1][2:0]};
bypass_mask_wmask_reg = _RANDOM[1'h1][10:3];
rdata_last_r = _RANDOM[1'h1][11];
rdata_hold_data_0 = _RANDOM[1'h1][13:12];
rdata_hold_data_1 = _RANDOM[1'h1][15:14];
rdata_hold_data_2 = _RANDOM[1'h1][17:16];
rdata_hold_data_3 = _RANDOM[1'h1][19:18];
rdata_hold_data_4 = _RANDOM[1'h1][21:20];
rdata_hold_data_5 = _RANDOM[1'h1][23:22];
rdata_hold_data_6 = _RANDOM[1'h1][25:24];
rdata_hold_data_7 = _RANDOM[1'h1][27:26];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
bypass_mask_need_check_reg_last_r = 1'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_6 array (
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (io_w_req_bits_setIdx),
.W0_en (io_w_req_valid),
.W0_clk (clock),
.W0_data
({io_w_req_bits_data_7,
io_w_req_bits_data_6,
io_w_req_bits_data_5,
io_w_req_bits_data_4,
io_w_req_bits_data_3,
io_w_req_bits_data_2,
io_w_req_bits_data_1,
io_w_req_bits_data_0}),
.W0_mask (io_w_req_bits_waymask)
);
assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;
assign io_r_resp_data_4 = rdata_last_r ? mem_rdata_4 : rdata_hold_data_4;
assign io_r_resp_data_5 = rdata_last_r ? mem_rdata_5 : rdata_hold_data_5;
assign io_r_resp_data_6 = rdata_last_r ? mem_rdata_6 : rdata_hold_data_6;
assign io_r_resp_data_7 = rdata_last_r ? mem_rdata_7 : rdata_hold_data_7;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_35(
input clock,
input reset,
input io_r_req_valid,
input [7:0] io_r_req_bits_setIdx,
output [5:0] io_r_resp_data_0,
output [5:0] io_r_resp_data_1,
output [5:0] io_r_resp_data_2,
output [5:0] io_r_resp_data_3,
input io_w_req_valid,
input [7:0] io_w_req_bits_setIdx,
input [5:0] io_w_req_bits_data_0,
input [5:0] io_w_req_bits_data_1,
input [5:0] io_w_req_bits_data_2,
input [5:0] io_w_req_bits_data_3,
input [3:0] io_w_req_bits_waymask
);
wire [23:0] _array_R0_data;
reg _resetState;
reg [7:0] _resetSet;
reg [5:0] bypass_wdata_r_0;
reg [5:0] bypass_wdata_r_1;
reg [5:0] bypass_wdata_r_2;
reg [5:0] bypass_wdata_r_3;
wire bypass_mask_need_check = io_r_req_valid & io_w_req_valid;
reg bypass_mask_need_check_reg_last_r;
reg [7:0] bypass_mask_waddr_reg;
reg [7:0] bypass_mask_raddr_reg;
reg [3:0] bypass_mask_wmask_reg;
wire [3:0] bypass_mask =
{4{bypass_mask_need_check_reg_last_r
& bypass_mask_waddr_reg == bypass_mask_raddr_reg}} & bypass_mask_wmask_reg;
wire [5:0] mem_rdata_0 = bypass_mask[0] ? bypass_wdata_r_0 : _array_R0_data[5:0];
wire [5:0] mem_rdata_1 = bypass_mask[1] ? bypass_wdata_r_1 : _array_R0_data[11:6];
wire [5:0] mem_rdata_2 = bypass_mask[2] ? bypass_wdata_r_2 : _array_R0_data[17:12];
wire [5:0] mem_rdata_3 = bypass_mask[3] ? bypass_wdata_r_3 : _array_R0_data[23:18];
reg rdata_last_r;
reg [5:0] rdata_hold_data_0;
reg [5:0] rdata_hold_data_1;
reg [5:0] rdata_hold_data_2;
reg [5:0] rdata_hold_data_3;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 8'h0;
bypass_mask_need_check_reg_last_r <= 1'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 8'(_resetSet + 8'h1);
if (bypass_mask_need_check | bypass_mask_need_check_reg_last_r)
bypass_mask_need_check_reg_last_r <= bypass_mask_need_check;
if (io_r_req_valid | rdata_last_r)
rdata_last_r <= io_r_req_valid;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_w_req_valid & io_r_req_valid) begin
bypass_wdata_r_0 <= io_w_req_bits_data_0;
bypass_wdata_r_1 <= io_w_req_bits_data_1;
bypass_wdata_r_2 <= io_w_req_bits_data_2;
bypass_wdata_r_3 <= io_w_req_bits_data_3;
end
if (bypass_mask_need_check) begin
bypass_mask_waddr_reg <= io_w_req_bits_setIdx;
bypass_mask_raddr_reg <= io_r_req_bits_setIdx;
bypass_mask_wmask_reg <= io_w_req_bits_waymask;
end
if (rdata_last_r) begin
rdata_hold_data_0 <= mem_rdata_0;
rdata_hold_data_1 <= mem_rdata_1;
rdata_hold_data_2 <= mem_rdata_2;
rdata_hold_data_3 <= mem_rdata_3;
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:2];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[2'h0][0];
_resetSet = _RANDOM[2'h0][8:1];
bypass_wdata_r_0 = _RANDOM[2'h0][14:9];
bypass_wdata_r_1 = _RANDOM[2'h0][20:15];
bypass_wdata_r_2 = _RANDOM[2'h0][26:21];
bypass_wdata_r_3 = {_RANDOM[2'h0][31:27], _RANDOM[2'h1][0]};
bypass_mask_need_check_reg_last_r = _RANDOM[2'h1][1];
bypass_mask_waddr_reg = _RANDOM[2'h1][9:2];
bypass_mask_raddr_reg = _RANDOM[2'h1][17:10];
bypass_mask_wmask_reg = _RANDOM[2'h1][21:18];
rdata_last_r = _RANDOM[2'h1][22];
rdata_hold_data_0 = _RANDOM[2'h1][28:23];
rdata_hold_data_1 = {_RANDOM[2'h1][31:29], _RANDOM[2'h2][2:0]};
rdata_hold_data_2 = _RANDOM[2'h2][8:3];
rdata_hold_data_3 = _RANDOM[2'h2][14:9];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 8'h0;
bypass_mask_need_check_reg_last_r = 1'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_7 array (
.R0_addr (io_r_req_bits_setIdx),
.R0_en (io_r_req_valid),
.R0_clk (clock),
.R0_data (_array_R0_data),
.W0_addr (_resetState ? _resetSet : io_w_req_bits_setIdx),
.W0_en (io_w_req_valid | _resetState),
.W0_clk (clock),
.W0_data
({_resetState ? 6'h0 : io_w_req_bits_data_3,
_resetState ? 6'h0 : io_w_req_bits_data_2,
_resetState ? 6'h0 : io_w_req_bits_data_1,
_resetState ? 6'h0 : io_w_req_bits_data_0}),
.W0_mask (_resetState ? 4'hF : io_w_req_bits_waymask)
);
assign io_r_resp_data_0 = rdata_last_r ? mem_rdata_0 : rdata_hold_data_0;
assign io_r_resp_data_1 = rdata_last_r ? mem_rdata_1 : rdata_hold_data_1;
assign io_r_resp_data_2 = rdata_last_r ? mem_rdata_2 : rdata_hold_data_2;
assign io_r_resp_data_3 = rdata_last_r ? mem_rdata_3 : rdata_hold_data_3;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_39(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target
);
wire [6:0] setIdx;
wire realRen;
wire wen;
wire [52:0] _array_0_RW0_rdata;
reg _resetState;
reg [6:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [52:0] rdata_hold_data_0;
wire [52:0] _rdata_T_0 = rdata_last_r ? _array_0_RW0_rdata : rdata_hold_data_0;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 7'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 7'(_resetSet + 7'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r)
rdata_hold_data_0 <= _array_0_RW0_rdata;
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:4];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[3'h0][0];
_resetSet = _RANDOM[3'h0][7:1];
rdata_last_r = _RANDOM[3'h2][24];
rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][13:0]};
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 7'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_0_0 array_0 (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_0_tag,
_resetState ? 2'h0 : io_w_req_bits_data_0_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_0_target}),
.RW0_rdata (_array_0_RW0_rdata)
);
assign io_r_resp_data_0_valid = _rdata_T_0[52];
assign io_r_resp_data_0_tag = _rdata_T_0[51:43];
assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];
assign io_r_resp_data_0_target = _rdata_T_0[40:0];
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_43(
input clock,
input reset,
input io_r_req_valid,
input [6:0] io_r_req_bits_setIdx,
output io_r_resp_data_0_valid,
output [8:0] io_r_resp_data_0_tag,
output [1:0] io_r_resp_data_0_ctr,
output [40:0] io_r_resp_data_0_target,
output io_r_resp_data_1_valid,
output [8:0] io_r_resp_data_1_tag,
output [1:0] io_r_resp_data_1_ctr,
output [40:0] io_r_resp_data_1_target,
input io_w_req_valid,
input [6:0] io_w_req_bits_setIdx,
input [8:0] io_w_req_bits_data_0_tag,
input [1:0] io_w_req_bits_data_0_ctr,
input [40:0] io_w_req_bits_data_0_target,
input [8:0] io_w_req_bits_data_1_tag,
input [1:0] io_w_req_bits_data_1_ctr,
input [40:0] io_w_req_bits_data_1_target,
input [1:0] io_w_req_bits_waymask
);
wire [6:0] setIdx;
wire realRen;
wire wen;
wire [105:0] _array_RW0_rdata;
reg _resetState;
reg [6:0] _resetSet;
assign wen = io_w_req_valid | _resetState;
assign realRen = io_r_req_valid & ~wen;
assign setIdx = _resetState ? _resetSet : io_w_req_bits_setIdx;
reg rdata_last_r;
reg [52:0] rdata_hold_data_0;
reg [52:0] rdata_hold_data_1;
wire [52:0] _rdata_T_0 = rdata_last_r ? _array_RW0_rdata[52:0] : rdata_hold_data_0;
wire [52:0] _rdata_T_1 = rdata_last_r ? _array_RW0_rdata[105:53] : rdata_hold_data_1;
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1;
_resetSet <= 7'h0;
rdata_last_r <= 1'h0;
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState;
if (_resetState)
_resetSet <= 7'(_resetSet + 7'h1);
if (realRen | rdata_last_r)
rdata_last_r <= realRen;
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (rdata_last_r) begin
rdata_hold_data_0 <= _array_RW0_rdata[52:0];
rdata_hold_data_1 <= _array_RW0_rdata[105:53];
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:8];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin
_RANDOM[i] = `RANDOM;
end
_resetState = _RANDOM[4'h0][0];
_resetSet = _RANDOM[4'h0][7:1];
rdata_last_r = _RANDOM[4'h4][25];
rdata_hold_data_0 = {_RANDOM[4'h4][31:26], _RANDOM[4'h5], _RANDOM[4'h6][14:0]};
rdata_hold_data_1 = {_RANDOM[4'h6][31:15], _RANDOM[4'h7], _RANDOM[4'h8][3:0]};
`endif // RANDOMIZE_REG_INIT
if (reset) begin
_resetState = 1'h1;
_resetSet = 7'h0;
rdata_last_r = 1'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_8 array (
.RW0_addr (wen ? setIdx : io_r_req_bits_setIdx),
.RW0_en (realRen | wen),
.RW0_clk (clock),
.RW0_wmode (wen),
.RW0_wdata
({~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_1_tag,
_resetState ? 2'h0 : io_w_req_bits_data_1_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_1_target,
~_resetState,
_resetState ? 9'h0 : io_w_req_bits_data_0_tag,
_resetState ? 2'h0 : io_w_req_bits_data_0_ctr,
_resetState ? 41'h0 : io_w_req_bits_data_0_target}),
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask)
);
assign io_r_resp_data_0_valid = _rdata_T_0[52];
assign io_r_resp_data_0_tag = _rdata_T_0[51:43];
assign io_r_resp_data_0_ctr = _rdata_T_0[42:41];
assign io_r_resp_data_0_target = _rdata_T_0[40:0];
assign io_r_resp_data_1_valid = _rdata_T_1[52];
assign io_r_resp_data_1_tag = _rdata_T_1[51:43];
assign io_r_resp_data_1_ctr = _rdata_T_1[42:41];
assign io_r_resp_data_1_target = _rdata_T_1[40:0];
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageBTable(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits,
output [1:0] io_s1_cnt_0,
output [1:0] io_s1_cnt_1,
input io_update_mask_0,
input io_update_mask_1,
input [40:0] io_update_pc,
input [1:0] io_update_cnt_0,
input [1:0] io_update_cnt_1,
input io_update_takens_0,
input io_update_takens_1
);
wire [1:0] newCtrs_1;
wire [1:0] newCtrs_0;
wire _wrbypass_io_hit;
wire _wrbypass_io_hit_data_0_valid;
wire [1:0] _wrbypass_io_hit_data_0_bits;
wire _wrbypass_io_hit_data_1_valid;
wire [1:0] _wrbypass_io_hit_data_1_bits;
wire [1:0] _bt_io_r_resp_data_0;
wire [1:0] _bt_io_r_resp_data_1;
reg doing_reset;
reg [10:0] resetRow;
reg [10:0] s1_idx;
wire _wrbypass_io_wen_T = io_update_mask_0 | io_update_mask_1;
wire [1:0] oldCtrs_0 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_1_valid : _wrbypass_io_hit_data_0_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_1_bits : _wrbypass_io_hit_data_0_bits)
: io_update_pc[1] ? io_update_cnt_1 : io_update_cnt_0;
wire [1:0] oldCtrs_1 =
_wrbypass_io_hit
& (io_update_pc[1] ? _wrbypass_io_hit_data_0_valid : _wrbypass_io_hit_data_1_valid)
? (io_update_pc[1] ? _wrbypass_io_hit_data_0_bits : _wrbypass_io_hit_data_1_bits)
: io_update_pc[1] ? io_update_cnt_0 : io_update_cnt_1;
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
assign newCtrs_0 =
(&oldCtrs_0) & _GEN
? 2'h3
: oldCtrs_0 == 2'h0 & ~_GEN
? 2'h0
: _GEN ? 2'(oldCtrs_0 + 2'h1) : 2'(oldCtrs_0 - 2'h1);
wire _GEN_0 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
assign newCtrs_1 =
(&oldCtrs_1) & _GEN_0
? 2'h3
: oldCtrs_1 == 2'h0 & ~_GEN_0
? 2'h0
: _GEN_0 ? 2'(oldCtrs_1 + 2'h1) : 2'(oldCtrs_1 - 2'h1);
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1;
resetRow <= 11'h0;
end
else begin
doing_reset <= resetRow != 11'h7FF & doing_reset;
resetRow <= 11'(resetRow + {10'h0, doing_reset});
end
end // always @(posedge, posedge)
always @(posedge clock) begin
if (io_req_valid)
s1_idx <= io_req_bits[11:1];
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0];
resetRow = _RANDOM[/*Zero width*/ 1'b0][11:1];
s1_idx = _RANDOM[/*Zero width*/ 1'b0][22:12];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
doing_reset = 1'h1;
resetRow = 11'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate_20 bt (
.clock (clock),
.reset (reset),
.io_r_req_valid (io_req_valid),
.io_r_req_bits_setIdx (io_req_bits[11:1]),
.io_r_resp_data_0 (_bt_io_r_resp_data_0),
.io_r_resp_data_1 (_bt_io_r_resp_data_1),
.io_w_req_valid (_wrbypass_io_wen_T | doing_reset),
.io_w_req_bits_setIdx (doing_reset ? resetRow : io_update_pc[11:1]),
.io_w_req_bits_data_0 (doing_reset ? 2'h2 : newCtrs_0),
.io_w_req_bits_data_1 (doing_reset ? 2'h2 : newCtrs_1),
.io_w_req_bits_waymask
(doing_reset
? 2'h3
: {io_update_mask_0 & io_update_pc[1] | io_update_mask_1 & ~(io_update_pc[1]),
io_update_mask_0 & ~(io_update_pc[1]) | io_update_mask_1 & io_update_pc[1]})
);
WrBypass_32 wrbypass (
.clock (clock),
.reset (reset),
.io_wen (_wrbypass_io_wen_T),
.io_write_idx (io_update_pc[11:1]),
.io_write_data_0 (io_update_pc[1] ? newCtrs_1 : newCtrs_0),
.io_write_data_1 (io_update_pc[1] ? newCtrs_0 : newCtrs_1),
.io_write_way_mask_0 (io_update_mask_0),
.io_write_way_mask_1 (io_update_mask_1),
.io_hit (_wrbypass_io_hit),
.io_hit_data_0_valid (_wrbypass_io_hit_data_0_valid),
.io_hit_data_0_bits (_wrbypass_io_hit_data_0_bits),
.io_hit_data_1_valid (_wrbypass_io_hit_data_1_valid),
.io_hit_data_1_bits (_wrbypass_io_hit_data_1_bits)
);
assign io_req_ready = ~doing_reset;
assign io_s1_cnt_0 =
(s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_0) | (s1_idx[0] ? _bt_io_r_resp_data_1 : 2'h0);
assign io_s1_cnt_1 =
(s1_idx[0] ? _bt_io_r_resp_data_0 : 2'h0) | (s1_idx[0] ? 2'h0 : _bt_io_r_resp_data_1);
endmodule

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rtl/BPUTop/TageTable.sv Normal file
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [7:0] io_req_bits_folded_hist_hist_14_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_7_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [7:0] io_update_folded_hist_hist_14_folded_hist,
input [6:0] io_update_folded_hist_hist_7_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [7:0] _GEN = io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_14_folded_hist;
wire s0_bank_req_1h_0 = _GEN[1:0] == 2'h0;
wire s0_bank_req_1h_1 = _GEN[1:0] == 2'h1;
wire s0_bank_req_1h_2 = _GEN[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
wire [8:0] _table_banks_3_io_r_req_bits_setIdx_T = {io_req_bits_pc[11:9], _GEN[7:2]};
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [7:0] _GEN_0 = io_update_pc[8:1] ^ io_update_folded_hist_hist_14_folded_hist;
wire [7:0] update_tag = _GEN_0 ^ {io_update_folded_hist_hist_7_folded_hist, 1'h0};
wire update_req_bank_1h_0 = _GEN_0[1:0] == 2'h0;
wire update_req_bank_1h_1 = _GEN_0[1:0] == 2'h1;
wire update_req_bank_1h_2 = _GEN_0[1:0] == 2'h2;
wire [8:0] update_idx_in_bank = {io_update_pc[11:9], _GEN_0[7:2]};
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(_GEN_0[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_1 = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_2 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_3 = (|_GEN_2) | _GEN_1;
wire _GEN_4 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN_1
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN_1 | _wrbypass_io_T_6 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_5 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_6 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_7 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_5
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_5 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN_1
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN_1 | _wrbypass_io_T_50 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_5
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_5 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN_1
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1 ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN_1 | _wrbypass_io_T_94 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_5
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_5 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_4
? (_GEN_1 ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN_1
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN_1
? 3'h0
: _GEN_1
? 3'(_wrbypass_io_T_138 + 3'h1)
: 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_2) & _GEN_1
? 3'h7
: _GEN_3 ? (_GEN_1 ? 3'(_GEN_2 + 3'h1) : 3'(_GEN_2 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN_1 | _wrbypass_io_T_138 == 3'h0 & ~_GEN_1)
: ~((&_GEN_2) & _GEN_1 | _GEN_2 == 3'h0 & ~_GEN_1)) | _GEN_4;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_7
? (_GEN_5 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_5
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_6) & _GEN_5
? 3'h7
: _GEN_6 == 3'h0 & ~_GEN_5
? 3'h0
: _GEN_5 ? 3'(_GEN_6 + 3'h1) : 3'(_GEN_6 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_5 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_5)
: ~((&_GEN_6) & _GEN_5 | _GEN_6 == 3'h0 & ~_GEN_5)) | _GEN_7;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <= _GEN ^ {io_req_bits_folded_hist_hist_7_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(_GEN[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx ({io_req_bits_pc[11:9], _GEN}),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx ({io_update_pc[11:9], _GEN_0}),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(_GEN[1:0]))),
.io_r_req_bits_setIdx (_table_banks_3_io_r_req_bits_setIdx_T),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx_in_bank),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(_GEN_0[1:0]))),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(_GEN_0[1:0]))),
.io_write_idx (update_idx_in_bank),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_1.sv Normal file
View File

@ -0,0 +1,754 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_1(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [6:0] io_req_bits_folded_hist_hist_15_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_4_folded_hist,
input [10:0] io_req_bits_folded_hist_hist_1_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [6:0] io_update_folded_hist_hist_15_folded_hist,
input [7:0] io_update_folded_hist_hist_4_folded_hist,
input [10:0] io_update_folded_hist_hist_1_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_1_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_1_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_4_folded_hist
^ {io_update_folded_hist_hist_15_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_4_folded_hist
^ {io_req_bits_folded_hist_hist_15_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_2.sv Normal file
View File

@ -0,0 +1,754 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_2(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [10:0] io_req_bits_folded_hist_hist_17_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_9_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_3_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [10:0] io_update_folded_hist_hist_17_folded_hist,
input [6:0] io_update_folded_hist_hist_9_folded_hist,
input [7:0] io_update_folded_hist_hist_3_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_17_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_17_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_3_folded_hist
^ {io_update_folded_hist_hist_9_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_3_folded_hist
^ {io_req_bits_folded_hist_hist_9_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

754
rtl/BPUTop/TageTable_3.sv Normal file
View File

@ -0,0 +1,754 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module TageTable_3(
input clock,
input reset,
output io_req_ready,
input io_req_valid,
input [40:0] io_req_bits_pc,
input [10:0] io_req_bits_folded_hist_hist_16_folded_hist,
input [7:0] io_req_bits_folded_hist_hist_8_folded_hist,
input [6:0] io_req_bits_folded_hist_hist_5_folded_hist,
output io_resps_0_valid,
output [2:0] io_resps_0_bits_ctr,
output io_resps_0_bits_u,
output io_resps_0_bits_unconf,
output io_resps_1_valid,
output [2:0] io_resps_1_bits_ctr,
output io_resps_1_bits_u,
output io_resps_1_bits_unconf,
input [40:0] io_update_pc,
input [10:0] io_update_folded_hist_hist_16_folded_hist,
input [7:0] io_update_folded_hist_hist_8_folded_hist,
input [6:0] io_update_folded_hist_hist_5_folded_hist,
input io_update_mask_0,
input io_update_mask_1,
input io_update_takens_0,
input io_update_takens_1,
input io_update_alloc_0,
input io_update_alloc_1,
input [2:0] io_update_oldCtrs_0,
input [2:0] io_update_oldCtrs_1,
input io_update_uMask_0,
input io_update_uMask_1,
input io_update_us_0,
input io_update_us_1,
input io_update_reset_u_0,
input io_update_reset_u_1
);
wire per_bank_not_silent_update_3_1;
wire per_bank_not_silent_update_3_0;
wire per_bank_not_silent_update_2_1;
wire per_bank_not_silent_update_2_0;
wire per_bank_not_silent_update_1_1;
wire per_bank_not_silent_update_1_0;
wire per_bank_not_silent_update_0_1;
wire per_bank_not_silent_update_0_0;
reg powerOnResetState;
wire _resp_invalid_by_write_T_6;
wire _bank_wrbypasses_3_1_io_hit;
wire _bank_wrbypasses_3_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_1_io_hit_data_0_bits;
wire _bank_wrbypasses_3_0_io_hit;
wire _bank_wrbypasses_3_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_3_0_io_hit_data_0_bits;
wire _bank_wrbypasses_2_1_io_hit;
wire _bank_wrbypasses_2_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_1_io_hit_data_0_bits;
wire _bank_wrbypasses_2_0_io_hit;
wire _bank_wrbypasses_2_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_2_0_io_hit_data_0_bits;
wire _bank_wrbypasses_1_1_io_hit;
wire _bank_wrbypasses_1_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_1_io_hit_data_0_bits;
wire _bank_wrbypasses_1_0_io_hit;
wire _bank_wrbypasses_1_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_1_0_io_hit_data_0_bits;
wire _bank_wrbypasses_0_1_io_hit;
wire _bank_wrbypasses_0_1_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_1_io_hit_data_0_bits;
wire _bank_wrbypasses_0_0_io_hit;
wire _bank_wrbypasses_0_0_io_hit_data_0_valid;
wire [2:0] _bank_wrbypasses_0_0_io_hit_data_0_bits;
wire _table_banks_3_io_r_req_ready;
wire _table_banks_3_io_r_resp_data_0_valid;
wire [7:0] _table_banks_3_io_r_resp_data_0_tag;
wire [2:0] _table_banks_3_io_r_resp_data_0_ctr;
wire _table_banks_3_io_r_resp_data_1_valid;
wire [7:0] _table_banks_3_io_r_resp_data_1_tag;
wire [2:0] _table_banks_3_io_r_resp_data_1_ctr;
wire _table_banks_2_io_r_req_ready;
wire _table_banks_2_io_r_resp_data_0_valid;
wire [7:0] _table_banks_2_io_r_resp_data_0_tag;
wire [2:0] _table_banks_2_io_r_resp_data_0_ctr;
wire _table_banks_2_io_r_resp_data_1_valid;
wire [7:0] _table_banks_2_io_r_resp_data_1_tag;
wire [2:0] _table_banks_2_io_r_resp_data_1_ctr;
wire _table_banks_1_io_r_req_ready;
wire _table_banks_1_io_r_resp_data_0_valid;
wire [7:0] _table_banks_1_io_r_resp_data_0_tag;
wire [2:0] _table_banks_1_io_r_resp_data_0_ctr;
wire _table_banks_1_io_r_resp_data_1_valid;
wire [7:0] _table_banks_1_io_r_resp_data_1_tag;
wire [2:0] _table_banks_1_io_r_resp_data_1_ctr;
wire _table_banks_0_io_r_req_ready;
wire _table_banks_0_io_r_resp_data_0_valid;
wire [7:0] _table_banks_0_io_r_resp_data_0_tag;
wire [2:0] _table_banks_0_io_r_resp_data_0_ctr;
wire _table_banks_0_io_r_resp_data_1_valid;
wire [7:0] _table_banks_0_io_r_resp_data_1_tag;
wire [2:0] _table_banks_0_io_r_resp_data_1_ctr;
wire _us_io_r_req_ready;
wire _us_io_r_resp_data_0;
wire _us_io_r_resp_data_1;
wire _us_extra_reset_T_1 = io_update_mask_0 | io_update_mask_1;
wire [10:0] s0_idx = io_req_bits_pc[11:1] ^ io_req_bits_folded_hist_hist_16_folded_hist;
wire s0_bank_req_1h_0 = s0_idx[1:0] == 2'h0;
wire s0_bank_req_1h_1 = s0_idx[1:0] == 2'h1;
wire s0_bank_req_1h_2 = s0_idx[1:0] == 2'h2;
wire _s1_bank_req_1h_T = ~powerOnResetState & io_req_valid;
reg [39:0] s1_unhashed_idx;
reg [7:0] s1_tag;
reg s1_bank_req_1h_0;
reg s1_bank_req_1h_1;
reg s1_bank_req_1h_2;
reg s1_bank_req_1h_3;
reg s1_bank_has_write_on_this_req_0;
reg s1_bank_has_write_on_this_req_1;
reg s1_bank_has_write_on_this_req_2;
reg s1_bank_has_write_on_this_req_3;
wire [2:0] _resp_selected_T_6 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_0_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_0_ctr : 3'h0);
wire [2:0] _resp_selected_T_27 =
(s1_bank_req_1h_0 ? _table_banks_0_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_1 ? _table_banks_1_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_2 ? _table_banks_2_io_r_resp_data_1_ctr : 3'h0)
| (s1_bank_req_1h_3 ? _table_banks_3_io_r_resp_data_1_ctr : 3'h0);
wire _unconf_selected_T_6 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_0_ctr == 3'h4
| _table_banks_0_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_0_ctr == 3'h4
| _table_banks_1_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_0_ctr == 3'h4
| _table_banks_2_io_r_resp_data_0_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_0_ctr == 3'h4
| _table_banks_3_io_r_resp_data_0_ctr == 3'h3);
wire _unconf_selected_T_13 =
s1_bank_req_1h_0
& (_table_banks_0_io_r_resp_data_1_ctr == 3'h4
| _table_banks_0_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_1
& (_table_banks_1_io_r_resp_data_1_ctr == 3'h4
| _table_banks_1_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_2
& (_table_banks_2_io_r_resp_data_1_ctr == 3'h4
| _table_banks_2_io_r_resp_data_1_ctr == 3'h3) | s1_bank_req_1h_3
& (_table_banks_3_io_r_resp_data_1_ctr == 3'h4
| _table_banks_3_io_r_resp_data_1_ctr == 3'h3);
wire _hit_selected_T_6 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_0_tag == s1_tag
& _table_banks_0_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_0_tag == s1_tag
& _table_banks_1_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_0_tag == s1_tag
& _table_banks_2_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_0_tag == s1_tag
& _table_banks_3_io_r_resp_data_0_valid & ~_resp_invalid_by_write_T_6;
wire _hit_selected_T_13 =
s1_bank_req_1h_0 & _table_banks_0_io_r_resp_data_1_tag == s1_tag
& _table_banks_0_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_1 & _table_banks_1_io_r_resp_data_1_tag == s1_tag
& _table_banks_1_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_2 & _table_banks_2_io_r_resp_data_1_tag == s1_tag
& _table_banks_2_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6
| s1_bank_req_1h_3 & _table_banks_3_io_r_resp_data_1_tag == s1_tag
& _table_banks_3_io_r_resp_data_1_valid & ~_resp_invalid_by_write_T_6;
assign _resp_invalid_by_write_T_6 =
s1_bank_req_1h_0 & s1_bank_has_write_on_this_req_0 | s1_bank_req_1h_1
& s1_bank_has_write_on_this_req_1 | s1_bank_req_1h_2 & s1_bank_has_write_on_this_req_2
| s1_bank_req_1h_3 & s1_bank_has_write_on_this_req_3;
wire [10:0] update_idx = io_update_pc[11:1] ^ io_update_folded_hist_hist_16_folded_hist;
wire [7:0] update_tag =
io_update_pc[8:1] ^ io_update_folded_hist_hist_8_folded_hist
^ {io_update_folded_hist_hist_5_folded_hist, 1'h0};
wire update_req_bank_1h_0 = update_idx[1:0] == 2'h0;
wire update_req_bank_1h_1 = update_idx[1:0] == 2'h1;
wire update_req_bank_1h_2 = update_idx[1:0] == 2'h2;
wire [1:0] per_bank_update_way_mask_0 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_0_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_0_0};
wire [1:0] per_bank_update_way_mask_1 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_1_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_1_0};
wire [1:0] per_bank_update_way_mask_2 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_2_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_2_0};
wire [1:0] per_bank_update_way_mask_3 =
{(io_update_pc[1] & io_update_mask_0 | ~(io_update_pc[1]) & io_update_mask_1)
& per_bank_not_silent_update_3_1,
(~(io_update_pc[1]) & io_update_mask_0 | io_update_pc[1] & io_update_mask_1)
& per_bank_not_silent_update_3_0};
wire _s1_bank_has_write_on_this_req_WIRE_0 =
(|per_bank_update_way_mask_0) & update_req_bank_1h_0;
wire _s1_bank_has_write_on_this_req_WIRE_1 =
(|per_bank_update_way_mask_1) & update_req_bank_1h_1;
wire _s1_bank_has_write_on_this_req_WIRE_2 =
(|per_bank_update_way_mask_2) & update_req_bank_1h_2;
wire _s1_bank_has_write_on_this_req_WIRE_3 =
(|per_bank_update_way_mask_3) & (&(update_idx[1:0]));
wire [2:0] _wrbypass_io_T_6 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_0_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid =
(~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_0_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN = io_update_pc[1] ? io_update_takens_1 : io_update_takens_0;
wire [2:0] _GEN_0 = io_update_pc[1] ? io_update_oldCtrs_1 : io_update_oldCtrs_0;
wire _GEN_1 = (|_GEN_0) | _GEN;
wire _GEN_2 = io_update_pc[1] ? io_update_alloc_1 : io_update_alloc_0;
wire [2:0] per_bank_update_wdata_0_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid
? ((&_wrbypass_io_T_6) & _GEN
? 3'h7
: _wrbypass_io_T_6 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_6 + 3'h1) : 3'(_wrbypass_io_T_6 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_0_0 =
(wrbypass_data_valid
? ~((&_wrbypass_io_T_6) & _GEN | _wrbypass_io_T_6 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_28 =
(io_update_pc[1] ? _bank_wrbypasses_0_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_0_1_io_hit_data_0_bits);
wire wrbypass_data_valid_1 =
(io_update_pc[1] & _bank_wrbypasses_0_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_0_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_0_1_io_hit_data_0_valid);
wire _GEN_3 = io_update_pc[1] ? io_update_takens_0 : io_update_takens_1;
wire [2:0] _GEN_4 = io_update_pc[1] ? io_update_oldCtrs_0 : io_update_oldCtrs_1;
wire _GEN_5 = io_update_pc[1] ? io_update_alloc_0 : io_update_alloc_1;
wire [2:0] per_bank_update_wdata_0_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_1
? ((&_wrbypass_io_T_28) & _GEN_3
? 3'h7
: _wrbypass_io_T_28 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_28 + 3'h1) : 3'(_wrbypass_io_T_28 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_0_1 =
(wrbypass_data_valid_1
? ~((&_wrbypass_io_T_28) & _GEN_3 | _wrbypass_io_T_28 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_50 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_1_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_2 =
(~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_1_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_2
? ((&_wrbypass_io_T_50) & _GEN
? 3'h7
: _wrbypass_io_T_50 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_50 + 3'h1) : 3'(_wrbypass_io_T_50 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_1_0 =
(wrbypass_data_valid_2
? ~((&_wrbypass_io_T_50) & _GEN | _wrbypass_io_T_50 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_72 =
(io_update_pc[1] ? _bank_wrbypasses_1_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_1_1_io_hit_data_0_bits);
wire wrbypass_data_valid_3 =
(io_update_pc[1] & _bank_wrbypasses_1_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_1_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_1_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_1_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_3
? ((&_wrbypass_io_T_72) & _GEN_3
? 3'h7
: _wrbypass_io_T_72 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_wrbypass_io_T_72 + 3'h1) : 3'(_wrbypass_io_T_72 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_1_1 =
(wrbypass_data_valid_3
? ~((&_wrbypass_io_T_72) & _GEN_3 | _wrbypass_io_T_72 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_94 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_2_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_4 =
(~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_2_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_4
? ((&_wrbypass_io_T_94) & _GEN
? 3'h7
: _wrbypass_io_T_94 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_94 + 3'h1) : 3'(_wrbypass_io_T_94 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_2_0 =
(wrbypass_data_valid_4
? ~((&_wrbypass_io_T_94) & _GEN | _wrbypass_io_T_94 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_116 =
(io_update_pc[1] ? _bank_wrbypasses_2_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_2_1_io_hit_data_0_bits);
wire wrbypass_data_valid_5 =
(io_update_pc[1] & _bank_wrbypasses_2_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_2_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_2_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_2_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_5
? ((&_wrbypass_io_T_116) & _GEN_3
? 3'h7
: _wrbypass_io_T_116 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_116 + 3'h1)
: 3'(_wrbypass_io_T_116 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_2_1 =
(wrbypass_data_valid_5
? ~((&_wrbypass_io_T_116) & _GEN_3 | _wrbypass_io_T_116 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
wire [2:0] _wrbypass_io_T_138 =
(io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_0_io_hit_data_0_bits)
| (io_update_pc[1] ? _bank_wrbypasses_3_1_io_hit_data_0_bits : 3'h0);
wire wrbypass_data_valid_6 =
(~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit)
& (~(io_update_pc[1]) & _bank_wrbypasses_3_0_io_hit_data_0_valid | io_update_pc[1]
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_0_ctr =
_GEN_2
? (_GEN ? 3'h4 : 3'h3)
: wrbypass_data_valid_6
? ((&_wrbypass_io_T_138) & _GEN
? 3'h7
: _wrbypass_io_T_138 == 3'h0 & ~_GEN
? 3'h0
: _GEN ? 3'(_wrbypass_io_T_138 + 3'h1) : 3'(_wrbypass_io_T_138 - 3'h1))
: (&_GEN_0) & _GEN
? 3'h7
: _GEN_1 ? (_GEN ? 3'(_GEN_0 + 3'h1) : 3'(_GEN_0 - 3'h1)) : 3'h0;
assign per_bank_not_silent_update_3_0 =
(wrbypass_data_valid_6
? ~((&_wrbypass_io_T_138) & _GEN | _wrbypass_io_T_138 == 3'h0 & ~_GEN)
: ~((&_GEN_0) & _GEN | _GEN_0 == 3'h0 & ~_GEN)) | _GEN_2;
wire [2:0] _wrbypass_io_T_160 =
(io_update_pc[1] ? _bank_wrbypasses_3_0_io_hit_data_0_bits : 3'h0)
| (io_update_pc[1] ? 3'h0 : _bank_wrbypasses_3_1_io_hit_data_0_bits);
wire wrbypass_data_valid_7 =
(io_update_pc[1] & _bank_wrbypasses_3_0_io_hit | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit)
& (io_update_pc[1] & _bank_wrbypasses_3_0_io_hit_data_0_valid | ~(io_update_pc[1])
& _bank_wrbypasses_3_1_io_hit_data_0_valid);
wire [2:0] per_bank_update_wdata_3_1_ctr =
_GEN_5
? (_GEN_3 ? 3'h4 : 3'h3)
: wrbypass_data_valid_7
? ((&_wrbypass_io_T_160) & _GEN_3
? 3'h7
: _wrbypass_io_T_160 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3
? 3'(_wrbypass_io_T_160 + 3'h1)
: 3'(_wrbypass_io_T_160 - 3'h1))
: (&_GEN_4) & _GEN_3
? 3'h7
: _GEN_4 == 3'h0 & ~_GEN_3
? 3'h0
: _GEN_3 ? 3'(_GEN_4 + 3'h1) : 3'(_GEN_4 - 3'h1);
assign per_bank_not_silent_update_3_1 =
(wrbypass_data_valid_7
? ~((&_wrbypass_io_T_160) & _GEN_3 | _wrbypass_io_T_160 == 3'h0 & ~_GEN_3)
: ~((&_GEN_4) & _GEN_3 | _GEN_4 == 3'h0 & ~_GEN_3)) | _GEN_5;
always @(posedge clock) begin
if (_s1_bank_req_1h_T) begin
s1_unhashed_idx <= io_req_bits_pc[40:1];
s1_tag <=
io_req_bits_pc[8:1] ^ io_req_bits_folded_hist_hist_8_folded_hist
^ {io_req_bits_folded_hist_hist_5_folded_hist, 1'h0};
s1_bank_req_1h_0 <= s0_bank_req_1h_0;
s1_bank_req_1h_1 <= s0_bank_req_1h_1;
s1_bank_req_1h_2 <= s0_bank_req_1h_2;
s1_bank_req_1h_3 <= &(s0_idx[1:0]);
end
if (io_req_valid) begin
s1_bank_has_write_on_this_req_0 <= _s1_bank_has_write_on_this_req_WIRE_0;
s1_bank_has_write_on_this_req_1 <= _s1_bank_has_write_on_this_req_WIRE_1;
s1_bank_has_write_on_this_req_2 <= _s1_bank_has_write_on_this_req_WIRE_2;
s1_bank_has_write_on_this_req_3 <= _s1_bank_has_write_on_this_req_WIRE_3;
end
end // always @(posedge)
always @(posedge clock or posedge reset) begin
if (reset)
powerOnResetState <= 1'h1;
else
powerOnResetState <=
~(_us_io_r_req_ready & _table_banks_0_io_r_req_ready
& _table_banks_1_io_r_req_ready & _table_banks_2_io_r_req_ready
& _table_banks_3_io_r_req_ready) & powerOnResetState;
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:3];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM[i[1:0]] = `RANDOM;
end
s1_unhashed_idx = {_RANDOM[2'h0], _RANDOM[2'h1][7:0]};
s1_tag = _RANDOM[2'h1][26:19];
s1_bank_req_1h_0 = _RANDOM[2'h3][4];
s1_bank_req_1h_1 = _RANDOM[2'h3][5];
s1_bank_req_1h_2 = _RANDOM[2'h3][6];
s1_bank_req_1h_3 = _RANDOM[2'h3][7];
s1_bank_has_write_on_this_req_0 = _RANDOM[2'h3][8];
s1_bank_has_write_on_this_req_1 = _RANDOM[2'h3][9];
s1_bank_has_write_on_this_req_2 = _RANDOM[2'h3][10];
s1_bank_has_write_on_this_req_3 = _RANDOM[2'h3][11];
powerOnResetState = _RANDOM[2'h3][12];
`endif // RANDOMIZE_REG_INIT
if (reset)
powerOnResetState = 1'h1;
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
FoldedSRAMTemplate us (
.clock (clock),
.reset (reset),
.io_r_req_ready (_us_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T),
.io_r_req_bits_setIdx (s0_idx),
.io_r_resp_data_0 (_us_io_r_resp_data_0),
.io_r_resp_data_1 (_us_io_r_resp_data_1),
.io_w_req_valid
(_us_extra_reset_T_1 & (io_update_uMask_0 | io_update_uMask_1)),
.io_w_req_bits_setIdx (update_idx),
.io_w_req_bits_data_0
(~(io_update_pc[1]) & io_update_us_0 | io_update_pc[1] & io_update_us_1),
.io_w_req_bits_data_1
(io_update_pc[1] & io_update_us_0 | ~(io_update_pc[1]) & io_update_us_1),
.io_w_req_bits_waymask
({io_update_pc[1] & io_update_uMask_0 | ~(io_update_pc[1]) & io_update_uMask_1,
~(io_update_pc[1]) & io_update_uMask_0 | io_update_pc[1] & io_update_uMask_1}),
.extra_reset
((io_update_reset_u_0 | io_update_reset_u_1) & _us_extra_reset_T_1)
);
FoldedSRAMTemplate_1 table_banks_0 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_0_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_0),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_0_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_0_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_0_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_0_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_0_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_0_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_0),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_0_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_0_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_0)
);
FoldedSRAMTemplate_1 table_banks_1 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_1_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_1),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_1_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_1_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_1_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_1_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_1_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_1_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_1),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_1_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_1_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_1)
);
FoldedSRAMTemplate_1 table_banks_2 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_2_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & s0_bank_req_1h_2),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_2_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_2_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_2_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_2_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_2_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_2_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_2),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_2_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_2_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_2)
);
FoldedSRAMTemplate_1 table_banks_3 (
.clock (clock),
.reset (reset),
.io_r_req_ready (_table_banks_3_io_r_req_ready),
.io_r_req_valid (_s1_bank_req_1h_T & (&(s0_idx[1:0]))),
.io_r_req_bits_setIdx (s0_idx[10:2]),
.io_r_resp_data_0_valid (_table_banks_3_io_r_resp_data_0_valid),
.io_r_resp_data_0_tag (_table_banks_3_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_table_banks_3_io_r_resp_data_0_ctr),
.io_r_resp_data_1_valid (_table_banks_3_io_r_resp_data_1_valid),
.io_r_resp_data_1_tag (_table_banks_3_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_table_banks_3_io_r_resp_data_1_ctr),
.io_w_req_valid (_s1_bank_has_write_on_this_req_WIRE_3),
.io_w_req_bits_setIdx (update_idx[10:2]),
.io_w_req_bits_data_0_tag (update_tag),
.io_w_req_bits_data_0_ctr (per_bank_update_wdata_3_0_ctr),
.io_w_req_bits_data_1_tag (update_tag),
.io_w_req_bits_data_1_ctr (per_bank_update_wdata_3_1_ctr),
.io_w_req_bits_waymask (per_bank_update_way_mask_3)
);
WrBypass bank_wrbypasses_0_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_0_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_0_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_0_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_0),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_0_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_0_1_ctr)),
.io_hit (_bank_wrbypasses_0_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_0_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_0_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_1_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_1_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_1_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_1),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_1_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_1_1_ctr)),
.io_hit (_bank_wrbypasses_1_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_1_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_1_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_2_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_2_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_2_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & update_req_bank_1h_2),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_2_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_2_1_ctr)),
.io_hit (_bank_wrbypasses_2_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_2_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_2_1_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_0 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_0 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_0_ctr)
| (io_update_pc[1] ? per_bank_update_wdata_3_1_ctr : 3'h0)),
.io_hit (_bank_wrbypasses_3_0_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_0_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_0_io_hit_data_0_bits)
);
WrBypass bank_wrbypasses_3_1 (
.clock (clock),
.reset (reset),
.io_wen (io_update_mask_1 & (&(update_idx[1:0]))),
.io_write_idx (update_idx[10:2]),
.io_write_data_0
((io_update_pc[1] ? per_bank_update_wdata_3_0_ctr : 3'h0)
| (io_update_pc[1] ? 3'h0 : per_bank_update_wdata_3_1_ctr)),
.io_hit (_bank_wrbypasses_3_1_io_hit),
.io_hit_data_0_valid (_bank_wrbypasses_3_1_io_hit_data_0_valid),
.io_hit_data_0_bits (_bank_wrbypasses_3_1_io_hit_data_0_bits)
);
assign io_req_ready = ~powerOnResetState;
assign io_resps_0_valid =
~(s1_unhashed_idx[0]) & _hit_selected_T_6 | s1_unhashed_idx[0] & _hit_selected_T_13;
assign io_resps_0_bits_ctr =
(s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_6)
| (s1_unhashed_idx[0] ? _resp_selected_T_27 : 3'h0);
assign io_resps_0_bits_u =
~(s1_unhashed_idx[0]) & _us_io_r_resp_data_0 | s1_unhashed_idx[0]
& _us_io_r_resp_data_1;
assign io_resps_0_bits_unconf =
~(s1_unhashed_idx[0]) & _unconf_selected_T_6 | s1_unhashed_idx[0]
& _unconf_selected_T_13;
assign io_resps_1_valid =
s1_unhashed_idx[0] & _hit_selected_T_6 | ~(s1_unhashed_idx[0]) & _hit_selected_T_13;
assign io_resps_1_bits_ctr =
(s1_unhashed_idx[0] ? _resp_selected_T_6 : 3'h0)
| (s1_unhashed_idx[0] ? 3'h0 : _resp_selected_T_27);
assign io_resps_1_bits_u =
s1_unhashed_idx[0] & _us_io_r_resp_data_0 | ~(s1_unhashed_idx[0])
& _us_io_r_resp_data_1;
assign io_resps_1_bits_unconf =
s1_unhashed_idx[0] & _unconf_selected_T_6 | ~(s1_unhashed_idx[0])
& _unconf_selected_T_13;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass(
input clock,
input reset,
input io_wen,
input [8:0] io_write_idx,
input [2:0] io_write_data_0,
output io_hit,
output io_hit_data_0_valid,
output [2:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
reg valids_0_0;
reg valids_1_0;
reg valids_2_0;
reg valids_3_0;
reg valids_4_0;
reg valids_5_0;
reg valids_6_0;
reg valids_7_0;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] hit_idx =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7;
reg [6:0] state_reg;
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};
wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN = enq_idx == 3'h0;
wire _GEN_0 = enq_idx == 3'h1;
wire _GEN_1 = enq_idx == 3'h2;
wire _GEN_2 = enq_idx == 3'h3;
wire _GEN_3 = enq_idx == 3'h4;
wire _GEN_4 = enq_idx == 3'h5;
wire _GEN_5 = enq_idx == 3'h6;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_1_0 <= 1'h0;
valids_2_0 <= 1'h0;
valids_3_0 <= 1'h0;
valids_4_0 <= 1'h0;
valids_5_0 <= 1'h0;
valids_6_0 <= 1'h0;
valids_7_0 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
state_reg <= 7'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= hit_idx == 3'h0 | valids_0_0;
valids_1_0 <= hit_idx == 3'h1 | valids_1_0;
valids_2_0 <= hit_idx == 3'h2 | valids_2_0;
valids_3_0 <= hit_idx == 3'h3 | valids_3_0;
valids_4_0 <= hit_idx == 3'h4 | valids_4_0;
valids_5_0 <= hit_idx == 3'h5 | valids_5_0;
valids_6_0 <= hit_idx == 3'h6 | valids_6_0;
valids_7_0 <= (&hit_idx) | valids_7_0;
end
else begin
valids_0_0 <= _GEN | ~_GEN & valids_0_0;
valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0;
valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0;
valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0;
valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0;
valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0;
valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0;
valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0;
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}};
end
ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0;
ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1;
ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2;
ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3;
ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4;
ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5;
ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6;
ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1];
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2];
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3];
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4];
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5];
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6];
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7];
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11];
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12];
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13];
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14];
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15];
state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_1_0 = 1'h0;
valids_2_0 = 1'h0;
valids_3_0 = 1'h0;
valids_4_0 = 1'h0;
valids_5_0 = 1'h0;
valids_6_0 = 1'h0;
valids_7_0 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
state_reg = 7'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_8x3 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_32(
input clock,
input reset,
input io_wen,
input [10:0] io_write_idx,
input [1:0] io_write_data_0,
input [1:0] io_write_data_1,
input io_write_way_mask_0,
input io_write_way_mask_1,
output io_hit,
output io_hit_data_0_valid,
output [1:0] io_hit_data_0_bits,
output io_hit_data_1_valid,
output [1:0] io_hit_data_1_bits
);
wire [3:0] _data_mem_ext_R0_data;
wire [3:0] _data_mem_ext_R1_data;
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
reg valids_0_0;
reg valids_0_1;
reg valids_1_0;
reg valids_1_1;
reg valids_2_0;
reg valids_2_1;
reg valids_3_0;
reg valids_3_1;
reg valids_4_0;
reg valids_4_1;
reg valids_5_0;
reg valids_5_1;
reg valids_6_0;
reg valids_6_1;
reg valids_7_0;
reg valids_7_1;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire [2:0] _hit_idx_T_2 =
{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] hit_idx =
{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
|(_hit_idx_T_2[2:1]),
_hit_idx_T_2[2] | _hit_idx_T_2[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7;
reg [6:0] state_reg;
wire [2:0] enq_idx =
{state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}};
wire _GEN = hit_idx == 3'h0;
wire _GEN_0 = hit_idx == 3'h1;
wire _GEN_1 = hit_idx == 3'h2;
wire _GEN_2 = hit_idx == 3'h3;
wire _GEN_3 = hit_idx == 3'h4;
wire _GEN_4 = hit_idx == 3'h5;
wire _GEN_5 = hit_idx == 3'h6;
wire [2:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN_6 = enq_idx == 3'h0;
wire _GEN_7 = enq_idx == 3'h1;
wire _GEN_8 = enq_idx == 3'h2;
wire _GEN_9 = enq_idx == 3'h3;
wire _GEN_10 = enq_idx == 3'h4;
wire _GEN_11 = enq_idx == 3'h5;
wire _GEN_12 = enq_idx == 3'h6;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_0_1 <= 1'h0;
valids_1_0 <= 1'h0;
valids_1_1 <= 1'h0;
valids_2_0 <= 1'h0;
valids_2_1 <= 1'h0;
valids_3_0 <= 1'h0;
valids_3_1 <= 1'h0;
valids_4_0 <= 1'h0;
valids_4_1 <= 1'h0;
valids_5_0 <= 1'h0;
valids_5_1 <= 1'h0;
valids_6_0 <= 1'h0;
valids_6_1 <= 1'h0;
valids_7_0 <= 1'h0;
valids_7_1 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
state_reg <= 7'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1;
valids_7_0 <= io_write_way_mask_0 & (&hit_idx) | valids_7_0;
valids_7_1 <= io_write_way_mask_1 & (&hit_idx) | valids_7_1;
end
else begin
valids_0_0 <= io_write_way_mask_0 & _GEN_6 | ~_GEN_6 & valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN_6 | ~_GEN_6 & valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_7 | ~_GEN_7 & valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_7 | ~_GEN_7 & valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_8 | ~_GEN_8 & valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_8 | ~_GEN_8 & valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_9 | ~_GEN_9 & valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_9 | ~_GEN_9 & valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_10 | ~_GEN_10 & valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_10 | ~_GEN_10 & valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_11 | ~_GEN_11 & valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_11 | ~_GEN_11 & valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_12 | ~_GEN_12 & valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_12 | ~_GEN_12 & valids_6_1;
valids_7_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_7_0;
valids_7_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_7_1;
end
state_reg <=
{~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}};
end
ever_written_0 <= io_wen & ~hit & (_GEN_6 | io_wen & _GEN_6) | ever_written_0;
ever_written_1 <= io_wen & ~hit & (_GEN_7 | io_wen & _GEN_7) | ever_written_1;
ever_written_2 <= io_wen & ~hit & (_GEN_8 | io_wen & _GEN_8) | ever_written_2;
ever_written_3 <= io_wen & ~hit & (_GEN_9 | io_wen & _GEN_9) | ever_written_3;
ever_written_4 <= io_wen & ~hit & (_GEN_10 | io_wen & _GEN_10) | ever_written_4;
ever_written_5 <= io_wen & ~hit & (_GEN_11 | io_wen & _GEN_11) | ever_written_5;
ever_written_6 <= io_wen & ~hit & (_GEN_12 | io_wen & _GEN_12) | ever_written_6;
ever_written_7 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_7;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0];
valids_0_1 = _RANDOM[/*Zero width*/ 1'b0][1];
valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][2];
valids_1_1 = _RANDOM[/*Zero width*/ 1'b0][3];
valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][4];
valids_2_1 = _RANDOM[/*Zero width*/ 1'b0][5];
valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][6];
valids_3_1 = _RANDOM[/*Zero width*/ 1'b0][7];
valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][8];
valids_4_1 = _RANDOM[/*Zero width*/ 1'b0][9];
valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][10];
valids_5_1 = _RANDOM[/*Zero width*/ 1'b0][11];
valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][12];
valids_6_1 = _RANDOM[/*Zero width*/ 1'b0][13];
valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][14];
valids_7_1 = _RANDOM[/*Zero width*/ 1'b0][15];
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][16];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][17];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][18];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][19];
ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][20];
ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][21];
ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][22];
ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][23];
state_reg = _RANDOM[/*Zero width*/ 1'b0][30:24];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_0_1 = 1'h0;
valids_1_0 = 1'h0;
valids_1_1 = 1'h0;
valids_2_0 = 1'h0;
valids_2_1 = 1'h0;
valids_3_0 = 1'h0;
valids_3_1 = 1'h0;
valids_4_0 = 1'h0;
valids_4_1 = 1'h0;
valids_5_0 = 1'h0;
valids_5_1 = 1'h0;
valids_6_0 = 1'h0;
valids_6_1 = 1'h0;
valids_7_0 = 1'h0;
valids_7_1 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
state_reg = 7'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_32 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_8x4 data_mem_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (hit_idx),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}),
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0})
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0;
assign io_hit_data_0_bits = _data_mem_ext_R1_data[1:0];
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1;
assign io_hit_data_1_bits = _data_mem_ext_R0_data[3:2];
endmodule

580
rtl/BPUTop/WrBypass_33.sv Normal file
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@ -0,0 +1,580 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_33(
input clock,
input reset,
input io_wen,
input [7:0] io_write_idx,
input [5:0] io_write_data_0,
input [5:0] io_write_data_1,
input io_write_way_mask_0,
input io_write_way_mask_1,
output io_hit,
output io_hit_data_0_valid,
output [5:0] io_hit_data_0_bits,
output io_hit_data_1_valid,
output [5:0] io_hit_data_1_bits
);
wire [11:0] _data_mem_ext_R0_data;
wire [11:0] _data_mem_ext_R1_data;
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
wire _idx_tag_cam_io_r_resp_0_4;
wire _idx_tag_cam_io_r_resp_0_5;
wire _idx_tag_cam_io_r_resp_0_6;
wire _idx_tag_cam_io_r_resp_0_7;
wire _idx_tag_cam_io_r_resp_0_8;
wire _idx_tag_cam_io_r_resp_0_9;
wire _idx_tag_cam_io_r_resp_0_10;
wire _idx_tag_cam_io_r_resp_0_11;
wire _idx_tag_cam_io_r_resp_0_12;
wire _idx_tag_cam_io_r_resp_0_13;
wire _idx_tag_cam_io_r_resp_0_14;
wire _idx_tag_cam_io_r_resp_0_15;
reg valids_0_0;
reg valids_0_1;
reg valids_1_0;
reg valids_1_1;
reg valids_2_0;
reg valids_2_1;
reg valids_3_0;
reg valids_3_1;
reg valids_4_0;
reg valids_4_1;
reg valids_5_0;
reg valids_5_1;
reg valids_6_0;
reg valids_6_1;
reg valids_7_0;
reg valids_7_1;
reg valids_8_0;
reg valids_8_1;
reg valids_9_0;
reg valids_9_1;
reg valids_10_0;
reg valids_10_1;
reg valids_11_0;
reg valids_11_1;
reg valids_12_0;
reg valids_12_1;
reg valids_13_0;
reg valids_13_1;
reg valids_14_0;
reg valids_14_1;
reg valids_15_0;
reg valids_15_1;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
reg ever_written_4;
reg ever_written_5;
reg ever_written_6;
reg ever_written_7;
reg ever_written_8;
reg ever_written_9;
reg ever_written_10;
reg ever_written_11;
reg ever_written_12;
reg ever_written_13;
reg ever_written_14;
reg ever_written_15;
wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4;
wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5;
wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6;
wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7;
wire hits_oh_8 = _idx_tag_cam_io_r_resp_0_8 & ever_written_8;
wire hits_oh_9 = _idx_tag_cam_io_r_resp_0_9 & ever_written_9;
wire hits_oh_10 = _idx_tag_cam_io_r_resp_0_10 & ever_written_10;
wire hits_oh_11 = _idx_tag_cam_io_r_resp_0_11 & ever_written_11;
wire hits_oh_12 = _idx_tag_cam_io_r_resp_0_12 & ever_written_12;
wire hits_oh_13 = _idx_tag_cam_io_r_resp_0_13 & ever_written_13;
wire hits_oh_14 = _idx_tag_cam_io_r_resp_0_14 & ever_written_14;
wire hits_oh_15 = _idx_tag_cam_io_r_resp_0_15 & ever_written_15;
wire [6:0] _hit_idx_T_2 =
{hits_oh_15, hits_oh_14, hits_oh_13, hits_oh_12, hits_oh_11, hits_oh_10, hits_oh_9}
| {hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4, hits_oh_3, hits_oh_2, hits_oh_1};
wire [2:0] _hit_idx_T_4 = _hit_idx_T_2[6:4] | _hit_idx_T_2[2:0];
wire [3:0] hit_idx =
{|{hits_oh_15,
hits_oh_14,
hits_oh_13,
hits_oh_12,
hits_oh_11,
hits_oh_10,
hits_oh_9,
hits_oh_8},
|(_hit_idx_T_2[6:3]),
|(_hit_idx_T_4[2:1]),
_hit_idx_T_4[2] | _hit_idx_T_4[0]};
wire hit =
hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
| hits_oh_7 | hits_oh_8 | hits_oh_9 | hits_oh_10 | hits_oh_11 | hits_oh_12
| hits_oh_13 | hits_oh_14 | hits_oh_15;
reg [14:0] state_reg;
wire [3:0] enq_idx =
{state_reg[14],
state_reg[14]
? {state_reg[13],
state_reg[13]
? {state_reg[12], state_reg[12] ? state_reg[11] : state_reg[10]}
: {state_reg[9], state_reg[9] ? state_reg[8] : state_reg[7]}}
: {state_reg[6],
state_reg[6]
? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}};
wire _GEN = hit_idx == 4'h0;
wire _GEN_0 = hit_idx == 4'h1;
wire _GEN_1 = hit_idx == 4'h2;
wire _GEN_2 = hit_idx == 4'h3;
wire _GEN_3 = hit_idx == 4'h4;
wire _GEN_4 = hit_idx == 4'h5;
wire _GEN_5 = hit_idx == 4'h6;
wire _GEN_6 = hit_idx == 4'h7;
wire _GEN_7 = hit_idx == 4'h8;
wire _GEN_8 = hit_idx == 4'h9;
wire _GEN_9 = hit_idx == 4'hA;
wire _GEN_10 = hit_idx == 4'hB;
wire _GEN_11 = hit_idx == 4'hC;
wire _GEN_12 = hit_idx == 4'hD;
wire _GEN_13 = hit_idx == 4'hE;
wire [3:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
wire _GEN_14 = enq_idx == 4'h0;
wire _GEN_15 = enq_idx == 4'h1;
wire _GEN_16 = enq_idx == 4'h2;
wire _GEN_17 = enq_idx == 4'h3;
wire _GEN_18 = enq_idx == 4'h4;
wire _GEN_19 = enq_idx == 4'h5;
wire _GEN_20 = enq_idx == 4'h6;
wire _GEN_21 = enq_idx == 4'h7;
wire _GEN_22 = enq_idx == 4'h8;
wire _GEN_23 = enq_idx == 4'h9;
wire _GEN_24 = enq_idx == 4'hA;
wire _GEN_25 = enq_idx == 4'hB;
wire _GEN_26 = enq_idx == 4'hC;
wire _GEN_27 = enq_idx == 4'hD;
wire _GEN_28 = enq_idx == 4'hE;
always @(posedge clock or posedge reset) begin
if (reset) begin
valids_0_0 <= 1'h0;
valids_0_1 <= 1'h0;
valids_1_0 <= 1'h0;
valids_1_1 <= 1'h0;
valids_2_0 <= 1'h0;
valids_2_1 <= 1'h0;
valids_3_0 <= 1'h0;
valids_3_1 <= 1'h0;
valids_4_0 <= 1'h0;
valids_4_1 <= 1'h0;
valids_5_0 <= 1'h0;
valids_5_1 <= 1'h0;
valids_6_0 <= 1'h0;
valids_6_1 <= 1'h0;
valids_7_0 <= 1'h0;
valids_7_1 <= 1'h0;
valids_8_0 <= 1'h0;
valids_8_1 <= 1'h0;
valids_9_0 <= 1'h0;
valids_9_1 <= 1'h0;
valids_10_0 <= 1'h0;
valids_10_1 <= 1'h0;
valids_11_0 <= 1'h0;
valids_11_1 <= 1'h0;
valids_12_0 <= 1'h0;
valids_12_1 <= 1'h0;
valids_13_0 <= 1'h0;
valids_13_1 <= 1'h0;
valids_14_0 <= 1'h0;
valids_14_1 <= 1'h0;
valids_15_0 <= 1'h0;
valids_15_1 <= 1'h0;
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
ever_written_4 <= 1'h0;
ever_written_5 <= 1'h0;
ever_written_6 <= 1'h0;
ever_written_7 <= 1'h0;
ever_written_8 <= 1'h0;
ever_written_9 <= 1'h0;
ever_written_10 <= 1'h0;
ever_written_11 <= 1'h0;
ever_written_12 <= 1'h0;
ever_written_13 <= 1'h0;
ever_written_14 <= 1'h0;
ever_written_15 <= 1'h0;
state_reg <= 15'h0;
end
else begin
if (io_wen) begin
if (hit) begin
valids_0_0 <= io_write_way_mask_0 & _GEN | valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN | valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_0 | valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_0 | valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_1 | valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_1 | valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_2 | valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_2 | valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_3 | valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_3 | valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_4 | valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_4 | valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_5 | valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_5 | valids_6_1;
valids_7_0 <= io_write_way_mask_0 & _GEN_6 | valids_7_0;
valids_7_1 <= io_write_way_mask_1 & _GEN_6 | valids_7_1;
valids_8_0 <= io_write_way_mask_0 & _GEN_7 | valids_8_0;
valids_8_1 <= io_write_way_mask_1 & _GEN_7 | valids_8_1;
valids_9_0 <= io_write_way_mask_0 & _GEN_8 | valids_9_0;
valids_9_1 <= io_write_way_mask_1 & _GEN_8 | valids_9_1;
valids_10_0 <= io_write_way_mask_0 & _GEN_9 | valids_10_0;
valids_10_1 <= io_write_way_mask_1 & _GEN_9 | valids_10_1;
valids_11_0 <= io_write_way_mask_0 & _GEN_10 | valids_11_0;
valids_11_1 <= io_write_way_mask_1 & _GEN_10 | valids_11_1;
valids_12_0 <= io_write_way_mask_0 & _GEN_11 | valids_12_0;
valids_12_1 <= io_write_way_mask_1 & _GEN_11 | valids_12_1;
valids_13_0 <= io_write_way_mask_0 & _GEN_12 | valids_13_0;
valids_13_1 <= io_write_way_mask_1 & _GEN_12 | valids_13_1;
valids_14_0 <= io_write_way_mask_0 & _GEN_13 | valids_14_0;
valids_14_1 <= io_write_way_mask_1 & _GEN_13 | valids_14_1;
valids_15_0 <= io_write_way_mask_0 & (&hit_idx) | valids_15_0;
valids_15_1 <= io_write_way_mask_1 & (&hit_idx) | valids_15_1;
end
else begin
valids_0_0 <= io_write_way_mask_0 & _GEN_14 | ~_GEN_14 & valids_0_0;
valids_0_1 <= io_write_way_mask_1 & _GEN_14 | ~_GEN_14 & valids_0_1;
valids_1_0 <= io_write_way_mask_0 & _GEN_15 | ~_GEN_15 & valids_1_0;
valids_1_1 <= io_write_way_mask_1 & _GEN_15 | ~_GEN_15 & valids_1_1;
valids_2_0 <= io_write_way_mask_0 & _GEN_16 | ~_GEN_16 & valids_2_0;
valids_2_1 <= io_write_way_mask_1 & _GEN_16 | ~_GEN_16 & valids_2_1;
valids_3_0 <= io_write_way_mask_0 & _GEN_17 | ~_GEN_17 & valids_3_0;
valids_3_1 <= io_write_way_mask_1 & _GEN_17 | ~_GEN_17 & valids_3_1;
valids_4_0 <= io_write_way_mask_0 & _GEN_18 | ~_GEN_18 & valids_4_0;
valids_4_1 <= io_write_way_mask_1 & _GEN_18 | ~_GEN_18 & valids_4_1;
valids_5_0 <= io_write_way_mask_0 & _GEN_19 | ~_GEN_19 & valids_5_0;
valids_5_1 <= io_write_way_mask_1 & _GEN_19 | ~_GEN_19 & valids_5_1;
valids_6_0 <= io_write_way_mask_0 & _GEN_20 | ~_GEN_20 & valids_6_0;
valids_6_1 <= io_write_way_mask_1 & _GEN_20 | ~_GEN_20 & valids_6_1;
valids_7_0 <= io_write_way_mask_0 & _GEN_21 | ~_GEN_21 & valids_7_0;
valids_7_1 <= io_write_way_mask_1 & _GEN_21 | ~_GEN_21 & valids_7_1;
valids_8_0 <= io_write_way_mask_0 & _GEN_22 | ~_GEN_22 & valids_8_0;
valids_8_1 <= io_write_way_mask_1 & _GEN_22 | ~_GEN_22 & valids_8_1;
valids_9_0 <= io_write_way_mask_0 & _GEN_23 | ~_GEN_23 & valids_9_0;
valids_9_1 <= io_write_way_mask_1 & _GEN_23 | ~_GEN_23 & valids_9_1;
valids_10_0 <= io_write_way_mask_0 & _GEN_24 | ~_GEN_24 & valids_10_0;
valids_10_1 <= io_write_way_mask_1 & _GEN_24 | ~_GEN_24 & valids_10_1;
valids_11_0 <= io_write_way_mask_0 & _GEN_25 | ~_GEN_25 & valids_11_0;
valids_11_1 <= io_write_way_mask_1 & _GEN_25 | ~_GEN_25 & valids_11_1;
valids_12_0 <= io_write_way_mask_0 & _GEN_26 | ~_GEN_26 & valids_12_0;
valids_12_1 <= io_write_way_mask_1 & _GEN_26 | ~_GEN_26 & valids_12_1;
valids_13_0 <= io_write_way_mask_0 & _GEN_27 | ~_GEN_27 & valids_13_0;
valids_13_1 <= io_write_way_mask_1 & _GEN_27 | ~_GEN_27 & valids_13_1;
valids_14_0 <= io_write_way_mask_0 & _GEN_28 | ~_GEN_28 & valids_14_0;
valids_14_1 <= io_write_way_mask_1 & _GEN_28 | ~_GEN_28 & valids_14_1;
valids_15_0 <= io_write_way_mask_0 & (&enq_idx) | ~(&enq_idx) & valids_15_0;
valids_15_1 <= io_write_way_mask_1 & (&enq_idx) | ~(&enq_idx) & valids_15_1;
end
state_reg <=
{~(state_reg_touch_way_sized[3]),
state_reg_touch_way_sized[3]
? {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[11],
state_reg_touch_way_sized[1]
? state_reg[10]
: ~(state_reg_touch_way_sized[0])}
: state_reg[12:10],
state_reg_touch_way_sized[2]
? state_reg[9:7]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[8],
state_reg_touch_way_sized[1]
? state_reg[7]
: ~(state_reg_touch_way_sized[0])}}
: state_reg[13:7],
state_reg_touch_way_sized[3]
? state_reg[6:0]
: {~(state_reg_touch_way_sized[2]),
state_reg_touch_way_sized[2]
? {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[4],
state_reg_touch_way_sized[1]
? state_reg[3]
: ~(state_reg_touch_way_sized[0])}
: state_reg[5:3],
state_reg_touch_way_sized[2]
? state_reg[2:0]
: {~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1]
? ~(state_reg_touch_way_sized[0])
: state_reg[1],
state_reg_touch_way_sized[1]
? state_reg[0]
: ~(state_reg_touch_way_sized[0])}}};
end
ever_written_0 <= io_wen & ~hit & (_GEN_14 | io_wen & _GEN_14) | ever_written_0;
ever_written_1 <= io_wen & ~hit & (_GEN_15 | io_wen & _GEN_15) | ever_written_1;
ever_written_2 <= io_wen & ~hit & (_GEN_16 | io_wen & _GEN_16) | ever_written_2;
ever_written_3 <= io_wen & ~hit & (_GEN_17 | io_wen & _GEN_17) | ever_written_3;
ever_written_4 <= io_wen & ~hit & (_GEN_18 | io_wen & _GEN_18) | ever_written_4;
ever_written_5 <= io_wen & ~hit & (_GEN_19 | io_wen & _GEN_19) | ever_written_5;
ever_written_6 <= io_wen & ~hit & (_GEN_20 | io_wen & _GEN_20) | ever_written_6;
ever_written_7 <= io_wen & ~hit & (_GEN_21 | io_wen & _GEN_21) | ever_written_7;
ever_written_8 <= io_wen & ~hit & (_GEN_22 | io_wen & _GEN_22) | ever_written_8;
ever_written_9 <= io_wen & ~hit & (_GEN_23 | io_wen & _GEN_23) | ever_written_9;
ever_written_10 <= io_wen & ~hit & (_GEN_24 | io_wen & _GEN_24) | ever_written_10;
ever_written_11 <= io_wen & ~hit & (_GEN_25 | io_wen & _GEN_25) | ever_written_11;
ever_written_12 <= io_wen & ~hit & (_GEN_26 | io_wen & _GEN_26) | ever_written_12;
ever_written_13 <= io_wen & ~hit & (_GEN_27 | io_wen & _GEN_27) | ever_written_13;
ever_written_14 <= io_wen & ~hit & (_GEN_28 | io_wen & _GEN_28) | ever_written_14;
ever_written_15 <=
io_wen & ~hit & ((&enq_idx) | io_wen & (&enq_idx)) | ever_written_15;
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM;
end
valids_0_0 = _RANDOM[1'h0][0];
valids_0_1 = _RANDOM[1'h0][1];
valids_1_0 = _RANDOM[1'h0][2];
valids_1_1 = _RANDOM[1'h0][3];
valids_2_0 = _RANDOM[1'h0][4];
valids_2_1 = _RANDOM[1'h0][5];
valids_3_0 = _RANDOM[1'h0][6];
valids_3_1 = _RANDOM[1'h0][7];
valids_4_0 = _RANDOM[1'h0][8];
valids_4_1 = _RANDOM[1'h0][9];
valids_5_0 = _RANDOM[1'h0][10];
valids_5_1 = _RANDOM[1'h0][11];
valids_6_0 = _RANDOM[1'h0][12];
valids_6_1 = _RANDOM[1'h0][13];
valids_7_0 = _RANDOM[1'h0][14];
valids_7_1 = _RANDOM[1'h0][15];
valids_8_0 = _RANDOM[1'h0][16];
valids_8_1 = _RANDOM[1'h0][17];
valids_9_0 = _RANDOM[1'h0][18];
valids_9_1 = _RANDOM[1'h0][19];
valids_10_0 = _RANDOM[1'h0][20];
valids_10_1 = _RANDOM[1'h0][21];
valids_11_0 = _RANDOM[1'h0][22];
valids_11_1 = _RANDOM[1'h0][23];
valids_12_0 = _RANDOM[1'h0][24];
valids_12_1 = _RANDOM[1'h0][25];
valids_13_0 = _RANDOM[1'h0][26];
valids_13_1 = _RANDOM[1'h0][27];
valids_14_0 = _RANDOM[1'h0][28];
valids_14_1 = _RANDOM[1'h0][29];
valids_15_0 = _RANDOM[1'h0][30];
valids_15_1 = _RANDOM[1'h0][31];
ever_written_0 = _RANDOM[1'h1][0];
ever_written_1 = _RANDOM[1'h1][1];
ever_written_2 = _RANDOM[1'h1][2];
ever_written_3 = _RANDOM[1'h1][3];
ever_written_4 = _RANDOM[1'h1][4];
ever_written_5 = _RANDOM[1'h1][5];
ever_written_6 = _RANDOM[1'h1][6];
ever_written_7 = _RANDOM[1'h1][7];
ever_written_8 = _RANDOM[1'h1][8];
ever_written_9 = _RANDOM[1'h1][9];
ever_written_10 = _RANDOM[1'h1][10];
ever_written_11 = _RANDOM[1'h1][11];
ever_written_12 = _RANDOM[1'h1][12];
ever_written_13 = _RANDOM[1'h1][13];
ever_written_14 = _RANDOM[1'h1][14];
ever_written_15 = _RANDOM[1'h1][15];
state_reg = _RANDOM[1'h1][30:16];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
valids_0_0 = 1'h0;
valids_0_1 = 1'h0;
valids_1_0 = 1'h0;
valids_1_1 = 1'h0;
valids_2_0 = 1'h0;
valids_2_1 = 1'h0;
valids_3_0 = 1'h0;
valids_3_1 = 1'h0;
valids_4_0 = 1'h0;
valids_4_1 = 1'h0;
valids_5_0 = 1'h0;
valids_5_1 = 1'h0;
valids_6_0 = 1'h0;
valids_6_1 = 1'h0;
valids_7_0 = 1'h0;
valids_7_1 = 1'h0;
valids_8_0 = 1'h0;
valids_8_1 = 1'h0;
valids_9_0 = 1'h0;
valids_9_1 = 1'h0;
valids_10_0 = 1'h0;
valids_10_1 = 1'h0;
valids_11_0 = 1'h0;
valids_11_1 = 1'h0;
valids_12_0 = 1'h0;
valids_12_1 = 1'h0;
valids_13_0 = 1'h0;
valids_13_1 = 1'h0;
valids_14_0 = 1'h0;
valids_14_1 = 1'h0;
valids_15_0 = 1'h0;
valids_15_1 = 1'h0;
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
ever_written_4 = 1'h0;
ever_written_5 = 1'h0;
ever_written_6 = 1'h0;
ever_written_7 = 1'h0;
ever_written_8 = 1'h0;
ever_written_9 = 1'h0;
ever_written_10 = 1'h0;
ever_written_11 = 1'h0;
ever_written_12 = 1'h0;
ever_written_13 = 1'h0;
ever_written_14 = 1'h0;
ever_written_15 = 1'h0;
state_reg = 15'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_33 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
.io_r_resp_0_8 (_idx_tag_cam_io_r_resp_0_8),
.io_r_resp_0_9 (_idx_tag_cam_io_r_resp_0_9),
.io_r_resp_0_10 (_idx_tag_cam_io_r_resp_0_10),
.io_r_resp_0_11 (_idx_tag_cam_io_r_resp_0_11),
.io_r_resp_0_12 (_idx_tag_cam_io_r_resp_0_12),
.io_r_resp_0_13 (_idx_tag_cam_io_r_resp_0_13),
.io_r_resp_0_14 (_idx_tag_cam_io_r_resp_0_14),
.io_r_resp_0_15 (_idx_tag_cam_io_r_resp_0_15),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_16x12 data_mem_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (_data_mem_ext_R0_data),
.R1_addr (hit_idx),
.R1_en (1'h1),
.R1_clk (clock),
.R1_data (_data_mem_ext_R1_data),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data ({io_write_data_1, io_write_data_0}),
.W0_mask ({io_write_way_mask_1, io_write_way_mask_0})
);
assign io_hit = hit;
assign io_hit_data_0_valid =
hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
& valids_6_0 | hits_oh_7 & valids_7_0 | hits_oh_8 & valids_8_0 | hits_oh_9
& valids_9_0 | hits_oh_10 & valids_10_0 | hits_oh_11 & valids_11_0 | hits_oh_12
& valids_12_0 | hits_oh_13 & valids_13_0 | hits_oh_14 & valids_14_0 | hits_oh_15
& valids_15_0;
assign io_hit_data_0_bits = _data_mem_ext_R1_data[5:0];
assign io_hit_data_1_valid =
hits_oh_0 & valids_0_1 | hits_oh_1 & valids_1_1 | hits_oh_2 & valids_2_1 | hits_oh_3
& valids_3_1 | hits_oh_4 & valids_4_1 | hits_oh_5 & valids_5_1 | hits_oh_6
& valids_6_1 | hits_oh_7 & valids_7_1 | hits_oh_8 & valids_8_1 | hits_oh_9
& valids_9_1 | hits_oh_10 & valids_10_1 | hits_oh_11 & valids_11_1 | hits_oh_12
& valids_12_1 | hits_oh_13 & valids_13_1 | hits_oh_14 & valids_14_1 | hits_oh_15
& valids_15_1;
assign io_hit_data_1_bits = _data_mem_ext_R0_data[11:6];
endmodule

157
rtl/BPUTop/WrBypass_41.sv Normal file
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@ -0,0 +1,157 @@
// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_41(
input clock,
input reset,
input io_wen,
input [7:0] io_write_idx,
input [1:0] io_write_data_0,
output io_hit,
output [1:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;
reg [2:0] state_reg;
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};
wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
state_reg <= 3'h0;
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0;
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1;
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2;
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3;
if (io_wen)
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
state_reg = 3'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_41 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_4x2 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_43(
input clock,
input reset,
input io_wen,
input [8:0] io_write_idx,
input [1:0] io_write_data_0,
output io_hit,
output [1:0] io_hit_data_0_bits
);
wire _idx_tag_cam_io_r_resp_0_0;
wire _idx_tag_cam_io_r_resp_0_1;
wire _idx_tag_cam_io_r_resp_0_2;
wire _idx_tag_cam_io_r_resp_0_3;
reg ever_written_0;
reg ever_written_1;
reg ever_written_2;
reg ever_written_3;
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1;
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2;
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3;
wire [1:0] hit_idx = {|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1};
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3;
reg [2:0] state_reg;
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]};
wire [1:0] state_reg_touch_way_sized = hit ? hit_idx : enq_idx;
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0;
ever_written_1 <= 1'h0;
ever_written_2 <= 1'h0;
ever_written_3 <= 1'h0;
state_reg <= 3'h0;
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0;
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1;
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2;
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3;
if (io_wen)
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])};
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_
`ifdef FIRRTL_BEFORE_INITIAL
`FIRRTL_BEFORE_INITIAL
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0];
initial begin
`ifdef INIT_RANDOM_PROLOG_
`INIT_RANDOM_PROLOG_
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM;
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4];
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5];
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6];
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7];
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8];
`endif // RANDOMIZE_REG_INIT
if (reset) begin
ever_written_0 = 1'h0;
ever_written_1 = 1'h0;
ever_written_2 = 1'h0;
ever_written_3 = 1'h0;
state_reg = 3'h0;
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL
`FIRRTL_AFTER_INITIAL
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_43 idx_tag_cam (
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit),
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx)
);
data_mem_0_4x2 data_mem_0_ext (
.R0_addr (hit_idx),
.R0_en (1'h1),
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? hit_idx : enq_idx),
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_0_0(
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [52:0] RW0_wdata,
output [52:0] RW0_rdata
);
array_0_0_ext array_0_0_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule

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module array_0_0_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [52:0] RW0_wdata,
output [52:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [52:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {2 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<1;i=i+1) begin
ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53];
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [63:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[52:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_3(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata,
input [3:0] RW0_wmask
);
array_3_ext array_3_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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module array_3_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [3:0] RW0_wmask,
input [319:0] RW0_wdata,
output [319:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [319:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {10 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<4;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*80 +: 80] <= RW0_wdata[i*80 +: 80];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [319:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random, $random, $random, $random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[319:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_4(
input [7:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata,
input [15:0] RW0_wmask
);
array_4_ext array_4_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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module array_4_ext(
input RW0_clk,
input [7:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [15:0] RW0_wmask,
input [15:0] RW0_wdata,
output [15:0] RW0_rdata
);
reg reg_RW0_ren;
reg [7:0] reg_RW0_addr;
reg [15:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
ram[RW0_addr] <= (RW0_wmask & RW0_wdata) | (~RW0_wmask & ram[RW0_addr]);
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[15:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_5(
input [8:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_5_ext array_5_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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module array_5_ext(
input RW0_clk,
input [8:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [23:0] RW0_wdata,
output [23:0] RW0_rdata
);
reg reg_RW0_ren;
reg [8:0] reg_RW0_addr;
reg [23:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<2;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*12 +: 12] <= RW0_wdata[i*12 +: 12];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[23:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_6(
input [8:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [8:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [7:0] W0_mask
);
array_6_ext array_6_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

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module array_6_ext(
input W0_clk,
input [8:0] W0_addr,
input W0_en,
input [15:0] W0_data,
input [7:0] W0_mask,
input R0_clk,
input [8:0] R0_addr,
input R0_en,
output [15:0] R0_data
);
reg reg_R0_ren;
reg [8:0] reg_R0_addr;
reg [15:0] ram [511:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 512; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][1:0] <= W0_data[1:0];
if (W0_mask[1]) ram[W0_addr][3:2] <= W0_data[3:2];
if (W0_mask[2]) ram[W0_addr][5:4] <= W0_data[5:4];
if (W0_mask[3]) ram[W0_addr][7:6] <= W0_data[7:6];
if (W0_mask[4]) ram[W0_addr][9:8] <= W0_data[9:8];
if (W0_mask[5]) ram[W0_addr][11:10] <= W0_data[11:10];
if (W0_mask[6]) ram[W0_addr][13:12] <= W0_data[13:12];
if (W0_mask[7]) ram[W0_addr][15:14] <= W0_data[15:14];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[15:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_7(
input [7:0] R0_addr,
input R0_en,
input R0_clk,
output [23:0] R0_data,
input [7:0] W0_addr,
input W0_en,
input W0_clk,
input [23:0] W0_data,
input [3:0] W0_mask
);
array_7_ext array_7_ext (
.R0_addr (R0_addr),
.R0_en (R0_en),
.R0_clk (R0_clk),
.R0_data (R0_data),
.W0_addr (W0_addr),
.W0_en (W0_en),
.W0_clk (W0_clk),
.W0_data (W0_data),
.W0_mask (W0_mask)
);
endmodule

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module array_7_ext(
input W0_clk,
input [7:0] W0_addr,
input W0_en,
input [23:0] W0_data,
input [3:0] W0_mask,
input R0_clk,
input [7:0] R0_addr,
input R0_en,
output [23:0] R0_data
);
reg reg_R0_ren;
reg [7:0] reg_R0_addr;
reg [23:0] ram [255:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 256; initvar = initvar+1)
ram[initvar] = {1 {$random}};
reg_R0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge R0_clk)
reg_R0_ren <= R0_en;
always @(posedge R0_clk)
if (R0_en) reg_R0_addr <= R0_addr;
always @(posedge W0_clk)
if (W0_en) begin
if (W0_mask[0]) ram[W0_addr][5:0] <= W0_data[5:0];
if (W0_mask[1]) ram[W0_addr][11:6] <= W0_data[11:6];
if (W0_mask[2]) ram[W0_addr][17:12] <= W0_data[17:12];
if (W0_mask[3]) ram[W0_addr][23:18] <= W0_data[23:18];
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [31:0] R0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
R0_random = {$random};
reg_R0_ren = R0_random[0];
end
`endif
always @(posedge R0_clk) R0_random <= {$random};
assign R0_data = reg_R0_ren ? ram[reg_R0_addr] : R0_random[23:0];
`else
assign R0_data = ram[reg_R0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_8(
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [105:0] RW0_wdata,
output [105:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_8_ext array_8_ext (
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

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module array_8_ext(
input RW0_clk,
input [6:0] RW0_addr,
input RW0_en,
input RW0_wmode,
input [1:0] RW0_wmask,
input [105:0] RW0_wdata,
output [105:0] RW0_rdata
);
reg reg_RW0_ren;
reg [6:0] reg_RW0_addr;
reg [105:0] ram [127:0];
`ifdef RANDOMIZE_MEM_INIT
integer initvar;
initial begin
#`RANDOMIZE_DELAY begin end
for (initvar = 0; initvar < 128; initvar = initvar+1)
ram[initvar] = {4 {$random}};
reg_RW0_addr = {1 {$random}};
end
`endif
integer i;
always @(posedge RW0_clk)
reg_RW0_ren <= RW0_en && !RW0_wmode;
always @(posedge RW0_clk)
if (RW0_en && !RW0_wmode) reg_RW0_addr <= RW0_addr;
always @(posedge RW0_clk)
if (RW0_en && RW0_wmode) begin
for (i=0;i<2;i=i+1) begin
if (RW0_wmask[i]) begin
ram[RW0_addr][i*53 +: 53] <= RW0_wdata[i*53 +: 53];
end
end
end
`ifdef RANDOMIZE_GARBAGE_ASSIGN
reg [127:0] RW0_random;
`ifdef RANDOMIZE_MEM_INIT
initial begin
#`RANDOMIZE_DELAY begin end
RW0_random = {$random, $random, $random, $random};
reg_RW0_ren = RW0_random[0];
end
`endif
always @(posedge RW0_clk) RW0_random <= {$random, $random, $random, $random};
assign RW0_rdata = reg_RW0_ren ? ram[reg_RW0_addr] : RW0_random[105:0];
`else
assign RW0_rdata = ram[reg_RW0_addr];
`endif
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_16x16(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [3:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[3:0]] = _RANDOM_MEM[15:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_32x16(
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [4:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:31];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
if (W1_en & 1'h1)
Memory[W1_addr] <= W1_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[4:0]] = _RANDOM_MEM[15:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx;
endmodule

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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_4x2(
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [1:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [1:0] W0_data
);
reg [1:0] Memory[0:3];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[1:0]] = _RANDOM_MEM[1:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 2'bx;
endmodule

89
rtl/BPUTop/data_mem_0_8x3.sv Normal file
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_8x3(
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [2:0] R0_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [2:0] W0_data
);
reg [2:0] Memory[0:7];
always @(posedge W0_clk) begin
if (W0_en & 1'h1)
Memory[W0_addr] <= W0_data;
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[2:0]] = _RANDOM_MEM[2:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 3'bx;
endmodule

97
rtl/BPUTop/data_mem_16x12.sv Normal file
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_16x12(
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [11:0] R0_data,
input [3:0] R1_addr,
input R1_en,
input R1_clk,
output [11:0] R1_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [11:0] W0_data,
input [1:0] W0_mask
);
reg [11:0] Memory[0:15];
always @(posedge W0_clk) begin
if (W0_en & W0_mask[0])
Memory[W0_addr][32'h0 +: 6] <= W0_data[5:0];
if (W0_en & W0_mask[1])
Memory[W0_addr][32'h6 +: 6] <= W0_data[11:6];
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[3:0]] = _RANDOM_MEM[11:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 12'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 12'bx;
endmodule

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rtl/BPUTop/data_mem_8x4.sv Normal file
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// Generated by CIRCT firtool-1.62.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_8x4(
input [2:0] R0_addr,
input R0_en,
input R0_clk,
output [3:0] R0_data,
input [2:0] R1_addr,
input R1_en,
input R1_clk,
output [3:0] R1_data,
input [2:0] W0_addr,
input W0_en,
input W0_clk,
input [3:0] W0_data,
input [1:0] W0_mask
);
reg [3:0] Memory[0:7];
always @(posedge W0_clk) begin
if (W0_en & W0_mask[0])
Memory[W0_addr][32'h0 +: 2] <= W0_data[1:0];
if (W0_en & W0_mask[1])
Memory[W0_addr][32'h2 +: 2] <= W0_data[3:2];
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_
reg [31:0] _RANDOM_MEM;
initial begin
`INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_MEM_INIT
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM_MEM = `RANDOM;
Memory[i[2:0]] = _RANDOM_MEM[3:0];
end
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 4'bx;
assign R1_data = R1_en ? Memory[R1_addr] : 4'bx;
endmodule