40 lines
1.3 KiB
Diff
40 lines
1.3 KiB
Diff
From: Andrew Cooper <andrew.cooper3@citrix.com>
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Subject: x86/pv: Handle the Intel-specific MSR_MISC_ENABLE correctly
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This MSR doesn't exist on AMD hardware, and switching away from the safe
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functions in the common MSR path was an erroneous change.
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Partially revert the change.
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This is XSA-333.
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Fixes: 4fdc932b3cc ("x86/Intel: drop another 32-bit leftover")
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Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
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Reviewed-by: Jan Beulich <jbeulich@suse.com>
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Reviewed-by: Wei Liu <wl@xen.org>
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diff --git a/xen/arch/x86/pv/emul-priv-op.c b/xen/arch/x86/pv/emul-priv-op.c
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index efeb2a727e..6332c74b80 100644
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--- a/xen/arch/x86/pv/emul-priv-op.c
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+++ b/xen/arch/x86/pv/emul-priv-op.c
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@@ -924,7 +924,8 @@ static int read_msr(unsigned int reg, uint64_t *val,
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return X86EMUL_OKAY;
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case MSR_IA32_MISC_ENABLE:
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- rdmsrl(reg, *val);
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+ if ( rdmsr_safe(reg, *val) )
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+ break;
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*val = guest_misc_enable(*val);
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return X86EMUL_OKAY;
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@@ -1059,7 +1060,8 @@ static int write_msr(unsigned int reg, uint64_t val,
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break;
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case MSR_IA32_MISC_ENABLE:
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- rdmsrl(reg, temp);
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+ if ( rdmsr_safe(reg, temp) )
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+ break;
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if ( val != guest_misc_enable(temp) )
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goto invalid;
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return X86EMUL_OKAY;
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