6 lines
387 B
Plaintext
6 lines
387 B
Plaintext
|
Icarus Verilog is a Verilog simulation and synthesis tool. It operates as
|
||
|
|
a compiler, compiling source code written in Verilog (IEEE-1364) into some
|
||
|
|
target format. For batch simulation, the compiler can generate an intermediate
|
||
|
|
form called vvp assembly. This intermediate form is executed by the 'vvp'
|
||
|
|
command. For synthesis, the compiler generates netlists in the desired format.
|