23 lines
982 B
Plaintext
23 lines
982 B
Plaintext
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Yosys is a framework for Verilog RTL synthesis. It currently has
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extensive Verilog-2005 support and provides a basic set of synthesis
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algorithms for various application domains.
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Yosys can be adapted to perform any synthesis job by combining the
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existing passes (algorithms) using synthesis scripts and adding
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additional passes as needed by extending the yosys C++ code base.
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Yosys is free software licensed under the ISC license (a GPL
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compatible license that is similar in terms to the MIT license or
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the 2-clause BSD license).
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By default it compiles using gcc if you want to use clang set
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the environment variable CLANG=yes.
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If you want to enable GHDL set GHDL=yes, this requires the GHDL
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package.
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For enabling protobuf install protobuf3 and set PROTOBUF=yes.
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For building the python wrappers set PYTHON=yes.
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If you want to enable ABC for synthesis and verification of
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binary sequential logic circuits set ABCEXTERNAL=yes, this
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requires berkeley-abc package.
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