178 lines
4.1 KiB
C
178 lines
4.1 KiB
C
/* The CPM2 internal interrupt controller. It is usually
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* the only interrupt controller.
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* There are two 32-bit registers (high/low) for up to 64
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* possible interrupts.
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*
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* Now, the fun starts.....Interrupt Numbers DO NOT MAP
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* in a simple arithmetic fashion to mask or pending registers.
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* That is, interrupt 4 does not map to bit position 4.
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* We create two tables, indexed by vector number, to indicate
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* which register to use and which bit in the register to use.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <asm/immap_cpm2.h>
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#include <asm/mpc8260.h>
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#include "cpm2_pic.h"
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static u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* bit numbers do not match the docs, these are precomputed so the bit for
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* a given irq is (1 << irq_to_siubit[irq]) */
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static u_char irq_to_siubit[] = {
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0, 15, 14, 13, 12, 11, 10, 9,
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8, 7, 6, 5, 4, 3, 2, 1,
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2, 1, 0, 14, 13, 12, 11, 10,
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9, 8, 7, 6, 5, 4, 3, 0,
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31, 30, 29, 28, 27, 26, 25, 24,
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23, 22, 21, 20, 19, 18, 17, 16,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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};
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static void cpm2_mask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_unmask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_mask_and_ack(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr, *sipnr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << bit;
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}
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static void cpm2_end_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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/*
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* Work around large numbers of spurious IRQs on PowerPC 82xx
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* systems.
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*/
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mb();
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}
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}
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static struct hw_interrupt_type cpm2_pic = {
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.typename = " CPM2 SIU ",
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.enable = cpm2_unmask_irq,
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.disable = cpm2_mask_irq,
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.ack = cpm2_mask_and_ack,
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.end = cpm2_end_irq,
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};
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int cpm2_get_irq(void)
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{
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int irq;
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unsigned long bits;
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/* For CPM2, read the SIVEC register and shift the bits down
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* to get the irq number. */
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bits = cpm2_immr->im_intctl.ic_sivec;
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irq = bits >> 26;
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if (irq == 0)
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return(-1);
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return irq+CPM_IRQ_OFFSET;
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}
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void cpm2_init_IRQ(void)
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{
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int i;
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/* Clear the CPM IRQ controller, in case it has any bits set
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* from the bootloader
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*/
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/* Mask out everything */
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cpm2_immr->im_intctl.ic_simrh = 0x00000000;
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cpm2_immr->im_intctl.ic_simrl = 0x00000000;
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wmb();
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/* Ack everything */
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cpm2_immr->im_intctl.ic_sipnrh = 0xffffffff;
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cpm2_immr->im_intctl.ic_sipnrl = 0xffffffff;
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wmb();
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/* Dummy read of the vector */
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i = cpm2_immr->im_intctl.ic_sivec;
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rmb();
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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cpm2_immr->im_intctl.ic_sicr = 0;
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cpm2_immr->im_intctl.ic_scprrh = 0x05309770;
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cpm2_immr->im_intctl.ic_scprrl = 0x05309770;
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/* Enable chaining to OpenPIC, and make everything level
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*/
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for (i = 0; i < NR_CPM_INTS; i++) {
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irq_desc[i+CPM_IRQ_OFFSET].chip = &cpm2_pic;
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irq_desc[i+CPM_IRQ_OFFSET].status |= IRQ_LEVEL;
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}
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}
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