96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/****************************************************************************/
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/*
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* m52xxacr.h -- ColdFire version 2 core cache support
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*
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* (C) Copyright 2010, Greg Ungerer <gerg@snapgear.com>
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*/
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/****************************************************************************/
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#ifndef m52xxacr_h
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#define m52xxacr_h
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/****************************************************************************/
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/*
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* All varients of the ColdFire using version 2 cores have a similar
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* cache setup. Although not absolutely identical the cache register
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* definitions are compatible for all of them. Mostly they support a
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* configurable cache memory that can be instruction only, data only,
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* or split instruction and data. The exception is the very old version 2
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* core based parts, like the 5206(e), 5249 and 5272, which are instruction
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* cache only. Cache size varies from 2k up to 16k.
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*/
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/*
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* Define the Cache Control register flags.
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*/
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#define CACR_CENB 0x80000000 /* Enable cache */
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#define CACR_CDPI 0x10000000 /* Disable invalidation by CPUSHL */
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#define CACR_CFRZ 0x08000000 /* Cache freeze mode */
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#define CACR_CINV 0x01000000 /* Invalidate cache */
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#define CACR_DISI 0x00800000 /* Disable instruction cache */
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#define CACR_DISD 0x00400000 /* Disable data cache */
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#define CACR_INVI 0x00200000 /* Invalidate instruction cache */
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#define CACR_INVD 0x00100000 /* Invalidate data cache */
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#define CACR_CEIB 0x00000400 /* Non-cachable instruction burst */
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#define CACR_DCM 0x00000200 /* Default cache mode */
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#define CACR_DBWE 0x00000100 /* Buffered write enable */
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#define CACR_DWP 0x00000020 /* Write protection */
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#define CACR_EUSP 0x00000010 /* Enable separate user a7 */
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/*
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* Define the Access Control register flags.
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*/
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#define ACR_BASE_POS 24 /* Address Base (upper 8 bits) */
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#define ACR_MASK_POS 16 /* Address Mask (next 8 bits) */
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#define ACR_ENABLE 0x00008000 /* Enable this ACR */
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#define ACR_USER 0x00000000 /* Allow only user accesses */
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#define ACR_SUPER 0x00002000 /* Allow supervisor access only */
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#define ACR_ANY 0x00004000 /* Allow any access type */
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#define ACR_CENB 0x00000000 /* Caching of region enabled */
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#define ACR_CDIS 0x00000040 /* Caching of region disabled */
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#define ACR_BWE 0x00000020 /* Write buffer enabled */
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#define ACR_WPROTECT 0x00000004 /* Write protect region */
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/*
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* Set the cache controller settings we will use. On the cores that support
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* a split cache configuration we allow all the combinations at Kconfig
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* time. For those cores that only have an instruction cache we just set
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* that as on.
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*/
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#if defined(CONFIG_CACHE_I)
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#define CACHE_TYPE (CACR_DISD + CACR_EUSP)
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#define CACHE_INVTYPEI 0
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#elif defined(CONFIG_CACHE_D)
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#define CACHE_TYPE (CACR_DISI + CACR_EUSP)
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#define CACHE_INVTYPED 0
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#elif defined(CONFIG_CACHE_BOTH)
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#define CACHE_TYPE CACR_EUSP
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#define CACHE_INVTYPEI CACR_INVI
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#define CACHE_INVTYPED CACR_INVD
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#else
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/* This is the instruction cache only devices (no split cache, no eusp) */
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#define CACHE_TYPE 0
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#define CACHE_INVTYPEI 0
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#endif
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#define CACHE_INIT (CACR_CINV + CACHE_TYPE)
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#define CACHE_MODE (CACR_CENB + CACHE_TYPE + CACR_DCM)
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#define CACHE_INVALIDATE (CACHE_MODE + CACR_CINV)
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#if defined(CACHE_INVTYPEI)
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#define CACHE_INVALIDATEI (CACHE_MODE + CACR_CINV + CACHE_INVTYPEI)
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#endif
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#if defined(CACHE_INVTYPED)
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#define CACHE_INVALIDATED (CACHE_MODE + CACR_CINV + CACHE_INVTYPED)
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#endif
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#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
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(0x000f0000) + \
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(ACR_ENABLE + ACR_ANY + ACR_CENB + ACR_BWE))
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#define ACR1_MODE 0
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/****************************************************************************/
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#endif /* m52xxsim_h */
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