464 lines
11 KiB
C
464 lines
11 KiB
C
/* dma.c: DMA controller management on FR401 and the like
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*
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* Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <asm/dma.h>
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#include <asm/gpio-regs.h>
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#include <asm/irc-regs.h>
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#include <asm/cpu-irqs.h>
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struct frv_dma_channel {
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uint8_t flags;
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#define FRV_DMA_FLAGS_RESERVED 0x01
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#define FRV_DMA_FLAGS_INUSE 0x02
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#define FRV_DMA_FLAGS_PAUSED 0x04
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uint8_t cap; /* capabilities available */
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int irq; /* completion IRQ */
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uint32_t dreqbit;
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uint32_t dackbit;
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uint32_t donebit;
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const unsigned long ioaddr; /* DMA controller regs addr */
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const char *devname;
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dma_irq_handler_t handler;
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void *data;
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};
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#define __get_DMAC(IO,X) ({ *(volatile unsigned long *)((IO) + DMAC_##X##x); })
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#define __set_DMAC(IO,X,V) \
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do { \
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*(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
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mb(); \
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} while(0)
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#define ___set_DMAC(IO,X,V) \
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do { \
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*(volatile unsigned long *)((IO) + DMAC_##X##x) = (V); \
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} while(0)
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static struct frv_dma_channel frv_dma_channels[FRV_DMA_NCHANS] = {
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[0] = {
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.cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
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.irq = IRQ_CPU_DMA0,
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.dreqbit = SIR_DREQ0_INPUT,
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.dackbit = SOR_DACK0_OUTPUT,
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.donebit = SOR_DONE0_OUTPUT,
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.ioaddr = 0xfe000900,
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},
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[1] = {
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.cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK | FRV_DMA_CAP_DONE,
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.irq = IRQ_CPU_DMA1,
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.dreqbit = SIR_DREQ1_INPUT,
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.dackbit = SOR_DACK1_OUTPUT,
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.donebit = SOR_DONE1_OUTPUT,
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.ioaddr = 0xfe000980,
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},
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[2] = {
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.cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
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.irq = IRQ_CPU_DMA2,
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.dreqbit = SIR_DREQ2_INPUT,
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.dackbit = SOR_DACK2_OUTPUT,
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.ioaddr = 0xfe000a00,
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},
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[3] = {
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.cap = FRV_DMA_CAP_DREQ | FRV_DMA_CAP_DACK,
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.irq = IRQ_CPU_DMA3,
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.dreqbit = SIR_DREQ3_INPUT,
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.dackbit = SOR_DACK3_OUTPUT,
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.ioaddr = 0xfe000a80,
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},
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[4] = {
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.cap = FRV_DMA_CAP_DREQ,
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.irq = IRQ_CPU_DMA4,
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.dreqbit = SIR_DREQ4_INPUT,
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.ioaddr = 0xfe001000,
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},
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[5] = {
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.cap = FRV_DMA_CAP_DREQ,
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.irq = IRQ_CPU_DMA5,
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.dreqbit = SIR_DREQ5_INPUT,
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.ioaddr = 0xfe001080,
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},
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[6] = {
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.cap = FRV_DMA_CAP_DREQ,
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.irq = IRQ_CPU_DMA6,
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.dreqbit = SIR_DREQ6_INPUT,
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.ioaddr = 0xfe001100,
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},
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[7] = {
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.cap = FRV_DMA_CAP_DREQ,
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.irq = IRQ_CPU_DMA7,
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.dreqbit = SIR_DREQ7_INPUT,
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.ioaddr = 0xfe001180,
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},
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};
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static DEFINE_RWLOCK(frv_dma_channels_lock);
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unsigned int frv_dma_inprogress;
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#define frv_clear_dma_inprogress(channel) \
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(void)__atomic32_fetch_and(~(1 << (channel)), &frv_dma_inprogress);
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#define frv_set_dma_inprogress(channel) \
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(void)__atomic32_fetch_or(1 << (channel), &frv_dma_inprogress);
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/*****************************************************************************/
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/*
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* DMA irq handler - determine channel involved, grab status and call real handler
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*/
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static irqreturn_t dma_irq_handler(int irq, void *_channel)
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{
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struct frv_dma_channel *channel = _channel;
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frv_clear_dma_inprogress(channel - frv_dma_channels);
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return channel->handler(channel - frv_dma_channels,
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__get_DMAC(channel->ioaddr, CSTR),
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channel->data);
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} /* end dma_irq_handler() */
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/*****************************************************************************/
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/*
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* Determine which DMA controllers are present on this CPU
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*/
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void __init frv_dma_init(void)
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{
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unsigned long psr = __get_PSR();
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int num_dma, i;
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/* First, determine how many DMA channels are available */
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switch (PSR_IMPLE(psr)) {
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case PSR_IMPLE_FR405:
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case PSR_IMPLE_FR451:
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case PSR_IMPLE_FR501:
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case PSR_IMPLE_FR551:
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num_dma = FRV_DMA_8CHANS;
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break;
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case PSR_IMPLE_FR401:
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default:
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num_dma = FRV_DMA_4CHANS;
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break;
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}
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/* Now mark all of the non-existent channels as reserved */
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for(i = num_dma; i < FRV_DMA_NCHANS; i++)
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frv_dma_channels[i].flags = FRV_DMA_FLAGS_RESERVED;
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} /* end frv_dma_init() */
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/*****************************************************************************/
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/*
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* allocate a DMA controller channel and the IRQ associated with it
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*/
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int frv_dma_open(const char *devname,
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unsigned long dmamask,
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int dmacap,
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dma_irq_handler_t handler,
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unsigned long irq_flags,
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void *data)
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{
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struct frv_dma_channel *channel;
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int dma, ret;
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uint32_t val;
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write_lock(&frv_dma_channels_lock);
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ret = -ENOSPC;
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for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
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channel = &frv_dma_channels[dma];
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if (!test_bit(dma, &dmamask))
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continue;
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if ((channel->cap & dmacap) != dmacap)
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continue;
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if (!frv_dma_channels[dma].flags)
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goto found;
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}
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goto out;
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found:
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ret = request_irq(channel->irq, dma_irq_handler, irq_flags, devname, channel);
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if (ret < 0)
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goto out;
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/* okay, we've allocated all the resources */
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channel = &frv_dma_channels[dma];
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channel->flags |= FRV_DMA_FLAGS_INUSE;
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channel->devname = devname;
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channel->handler = handler;
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channel->data = data;
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/* Now make sure we are set up for DMA and not GPIO */
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/* SIR bit must be set for DMA to work */
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__set_SIR(channel->dreqbit | __get_SIR());
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/* SOR bits depend on what the caller requests */
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val = __get_SOR();
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if(dmacap & FRV_DMA_CAP_DACK)
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val |= channel->dackbit;
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else
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val &= ~channel->dackbit;
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if(dmacap & FRV_DMA_CAP_DONE)
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val |= channel->donebit;
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else
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val &= ~channel->donebit;
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__set_SOR(val);
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ret = dma;
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out:
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write_unlock(&frv_dma_channels_lock);
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return ret;
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} /* end frv_dma_open() */
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EXPORT_SYMBOL(frv_dma_open);
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/*****************************************************************************/
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/*
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* close a DMA channel and its associated interrupt
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*/
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void frv_dma_close(int dma)
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{
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struct frv_dma_channel *channel = &frv_dma_channels[dma];
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unsigned long flags;
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write_lock_irqsave(&frv_dma_channels_lock, flags);
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free_irq(channel->irq, channel);
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frv_dma_stop(dma);
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channel->flags &= ~FRV_DMA_FLAGS_INUSE;
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write_unlock_irqrestore(&frv_dma_channels_lock, flags);
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} /* end frv_dma_close() */
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EXPORT_SYMBOL(frv_dma_close);
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/*****************************************************************************/
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/*
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* set static configuration on a DMA channel
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*/
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void frv_dma_config(int dma, unsigned long ccfr, unsigned long cctr, unsigned long apr)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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___set_DMAC(ioaddr, CCFR, ccfr);
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___set_DMAC(ioaddr, CCTR, cctr);
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___set_DMAC(ioaddr, APR, apr);
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mb();
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} /* end frv_dma_config() */
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EXPORT_SYMBOL(frv_dma_config);
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/*****************************************************************************/
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/*
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* start a DMA channel
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*/
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void frv_dma_start(int dma,
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unsigned long sba, unsigned long dba,
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unsigned long pix, unsigned long six, unsigned long bcl)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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___set_DMAC(ioaddr, SBA, sba);
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___set_DMAC(ioaddr, DBA, dba);
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___set_DMAC(ioaddr, PIX, pix);
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___set_DMAC(ioaddr, SIX, six);
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___set_DMAC(ioaddr, BCL, bcl);
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___set_DMAC(ioaddr, CSTR, 0);
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mb();
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__set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
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frv_set_dma_inprogress(dma);
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} /* end frv_dma_start() */
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EXPORT_SYMBOL(frv_dma_start);
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/*****************************************************************************/
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/*
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* restart a DMA channel that's been stopped in circular addressing mode by comparison-end
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*/
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void frv_dma_restart_circular(int dma, unsigned long six)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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___set_DMAC(ioaddr, SIX, six);
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___set_DMAC(ioaddr, CSTR, __get_DMAC(ioaddr, CSTR) & ~DMAC_CSTRx_CE);
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mb();
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__set_DMAC(ioaddr, CCTR, __get_DMAC(ioaddr, CCTR) | DMAC_CCTRx_ACT);
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frv_set_dma_inprogress(dma);
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} /* end frv_dma_restart_circular() */
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EXPORT_SYMBOL(frv_dma_restart_circular);
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/*****************************************************************************/
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/*
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* stop a DMA channel
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*/
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void frv_dma_stop(int dma)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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uint32_t cctr;
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___set_DMAC(ioaddr, CSTR, 0);
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cctr = __get_DMAC(ioaddr, CCTR);
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cctr &= ~(DMAC_CCTRx_IE | DMAC_CCTRx_ACT);
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cctr |= DMAC_CCTRx_FC; /* fifo clear */
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__set_DMAC(ioaddr, CCTR, cctr);
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__set_DMAC(ioaddr, BCL, 0);
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frv_clear_dma_inprogress(dma);
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} /* end frv_dma_stop() */
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EXPORT_SYMBOL(frv_dma_stop);
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/*****************************************************************************/
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/*
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* test interrupt status of DMA channel
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*/
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int is_frv_dma_interrupting(int dma)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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return __get_DMAC(ioaddr, CSTR) & (1 << 23);
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} /* end is_frv_dma_interrupting() */
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EXPORT_SYMBOL(is_frv_dma_interrupting);
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/*****************************************************************************/
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/*
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* dump data about a DMA channel
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*/
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void frv_dma_dump(int dma)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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unsigned long cstr, pix, six, bcl;
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cstr = __get_DMAC(ioaddr, CSTR);
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pix = __get_DMAC(ioaddr, PIX);
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six = __get_DMAC(ioaddr, SIX);
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bcl = __get_DMAC(ioaddr, BCL);
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printk("DMA[%d] cstr=%lx pix=%lx six=%lx bcl=%lx\n", dma, cstr, pix, six, bcl);
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} /* end frv_dma_dump() */
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EXPORT_SYMBOL(frv_dma_dump);
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/*****************************************************************************/
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/*
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* pause all DMA controllers
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* - called by clock mangling routines
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* - caller must be holding interrupts disabled
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*/
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void frv_dma_pause_all(void)
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{
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struct frv_dma_channel *channel;
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unsigned long ioaddr;
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unsigned long cstr, cctr;
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int dma;
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write_lock(&frv_dma_channels_lock);
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for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
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channel = &frv_dma_channels[dma];
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if (!(channel->flags & FRV_DMA_FLAGS_INUSE))
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continue;
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ioaddr = channel->ioaddr;
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cctr = __get_DMAC(ioaddr, CCTR);
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if (cctr & DMAC_CCTRx_ACT) {
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cctr &= ~DMAC_CCTRx_ACT;
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__set_DMAC(ioaddr, CCTR, cctr);
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do {
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cstr = __get_DMAC(ioaddr, CSTR);
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} while (cstr & DMAC_CSTRx_BUSY);
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if (cstr & DMAC_CSTRx_FED)
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channel->flags |= FRV_DMA_FLAGS_PAUSED;
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frv_clear_dma_inprogress(dma);
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}
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}
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} /* end frv_dma_pause_all() */
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EXPORT_SYMBOL(frv_dma_pause_all);
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/*****************************************************************************/
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/*
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* resume paused DMA controllers
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* - called by clock mangling routines
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* - caller must be holding interrupts disabled
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*/
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void frv_dma_resume_all(void)
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{
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struct frv_dma_channel *channel;
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unsigned long ioaddr;
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unsigned long cstr, cctr;
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int dma;
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for (dma = FRV_DMA_NCHANS - 1; dma >= 0; dma--) {
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channel = &frv_dma_channels[dma];
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if (!(channel->flags & FRV_DMA_FLAGS_PAUSED))
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continue;
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ioaddr = channel->ioaddr;
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cstr = __get_DMAC(ioaddr, CSTR);
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cstr &= ~(DMAC_CSTRx_FED | DMAC_CSTRx_INT);
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__set_DMAC(ioaddr, CSTR, cstr);
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cctr = __get_DMAC(ioaddr, CCTR);
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cctr |= DMAC_CCTRx_ACT;
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__set_DMAC(ioaddr, CCTR, cctr);
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channel->flags &= ~FRV_DMA_FLAGS_PAUSED;
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frv_set_dma_inprogress(dma);
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}
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write_unlock(&frv_dma_channels_lock);
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} /* end frv_dma_resume_all() */
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EXPORT_SYMBOL(frv_dma_resume_all);
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/*****************************************************************************/
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/*
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* dma status clear
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*/
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void frv_dma_status_clear(int dma)
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{
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unsigned long ioaddr = frv_dma_channels[dma].ioaddr;
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uint32_t cctr;
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___set_DMAC(ioaddr, CSTR, 0);
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cctr = __get_DMAC(ioaddr, CCTR);
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} /* end frv_dma_status_clear() */
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EXPORT_SYMBOL(frv_dma_status_clear);
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