499 lines
14 KiB
C
499 lines
14 KiB
C
/*
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* OMAP MPUSS low power code
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*
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* Copyright (C) 2011 Texas Instruments, Inc.
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* OMAP4430 MPUSS mainly consists of dual Cortex-A9 with per-CPU
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* Local timer and Watchdog, GIC, SCU, PL310 L2 cache controller,
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* CPU0 and CPU1 LPRM modules.
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* CPU0, CPU1 and MPUSS each have there own power domain and
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* hence multiple low power combinations of MPUSS are possible.
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*
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* The CPU0 and CPU1 can't support Closed switch Retention (CSWR)
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* because the mode is not supported by hw constraints of dormant
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* mode. While waking up from the dormant mode, a reset signal
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* to the Cortex-A9 processor must be asserted by the external
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* power controller.
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*
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* With architectural inputs and hardware recommendations, only
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* below modes are supported from power gain vs latency point of view.
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*
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* CPU0 CPU1 MPUSS
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* ----------------------------------------------
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* ON ON ON
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* ON(Inactive) OFF ON(Inactive)
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* OFF OFF CSWR
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* OFF OFF OSWR
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* OFF OFF OFF(Device OFF *TBD)
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* ----------------------------------------------
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*
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* Note: CPU0 is the master core and it is the last CPU to go down
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* and first to wake-up when MPUSS low power states are excercised
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/errno.h>
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#include <linux/linkage.h>
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#include <linux/smp.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/smp_scu.h>
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#include <asm/pgalloc.h>
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#include <asm/suspend.h>
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#include <asm/virt.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "soc.h"
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#include "common.h"
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#include "omap44xx.h"
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#include "omap4-sar-layout.h"
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#include "pm.h"
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#include "prcm_mpu44xx.h"
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#include "prcm_mpu54xx.h"
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#include "prminst44xx.h"
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#include "prcm44xx.h"
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#include "prm44xx.h"
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#include "prm-regbits-44xx.h"
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static void __iomem *sar_base;
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static u32 old_cpu1_ns_pa_addr;
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#if defined(CONFIG_PM) && defined(CONFIG_SMP)
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struct omap4_cpu_pm_info {
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struct powerdomain *pwrdm;
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void __iomem *scu_sar_addr;
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void __iomem *wkup_sar_addr;
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void __iomem *l2x0_sar_addr;
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};
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/**
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* struct cpu_pm_ops - CPU pm operations
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* @finish_suspend: CPU suspend finisher function pointer
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* @resume: CPU resume function pointer
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* @scu_prepare: CPU Snoop Control program function pointer
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* @hotplug_restart: CPU restart function pointer
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*
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* Structure holds functions pointer for CPU low power operations like
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* suspend, resume and scu programming.
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*/
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struct cpu_pm_ops {
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int (*finish_suspend)(unsigned long cpu_state);
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void (*resume)(void);
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void (*scu_prepare)(unsigned int cpu_id, unsigned int cpu_state);
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void (*hotplug_restart)(void);
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};
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static DEFINE_PER_CPU(struct omap4_cpu_pm_info, omap4_pm_info);
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static struct powerdomain *mpuss_pd;
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static u32 cpu_context_offset;
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static int default_finish_suspend(unsigned long cpu_state)
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{
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omap_do_wfi();
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return 0;
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}
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static void dummy_cpu_resume(void)
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{}
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static void dummy_scu_prepare(unsigned int cpu_id, unsigned int cpu_state)
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{}
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static struct cpu_pm_ops omap_pm_ops = {
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.finish_suspend = default_finish_suspend,
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.resume = dummy_cpu_resume,
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.scu_prepare = dummy_scu_prepare,
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.hotplug_restart = dummy_cpu_resume,
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};
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/*
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* Program the wakeup routine address for the CPU0 and CPU1
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* used for OFF or DORMANT wakeup.
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*/
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static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
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if (pm_info->wkup_sar_addr)
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writel_relaxed(addr, pm_info->wkup_sar_addr);
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}
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/*
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* Store the SCU power status value to scratchpad memory
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*/
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static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
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u32 scu_pwr_st;
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switch (cpu_state) {
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case PWRDM_POWER_RET:
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scu_pwr_st = SCU_PM_DORMANT;
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break;
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case PWRDM_POWER_OFF:
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scu_pwr_st = SCU_PM_POWEROFF;
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break;
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case PWRDM_POWER_ON:
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case PWRDM_POWER_INACTIVE:
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default:
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scu_pwr_st = SCU_PM_NORMAL;
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break;
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}
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if (pm_info->scu_sar_addr)
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writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
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}
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/* Helper functions for MPUSS OSWR */
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static inline void mpuss_clear_prev_logic_pwrst(void)
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{
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u32 reg;
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reg = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
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omap4_prminst_write_inst_reg(reg, OMAP4430_PRM_PARTITION,
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OMAP4430_PRM_MPU_INST, OMAP4_RM_MPU_MPU_CONTEXT_OFFSET);
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}
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static inline void cpu_clear_prev_logic_pwrst(unsigned int cpu_id)
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{
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u32 reg;
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if (cpu_id) {
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reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU1_INST,
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cpu_context_offset);
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omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU1_INST,
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cpu_context_offset);
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} else {
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reg = omap4_prcm_mpu_read_inst_reg(OMAP4430_PRCM_MPU_CPU0_INST,
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cpu_context_offset);
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omap4_prcm_mpu_write_inst_reg(reg, OMAP4430_PRCM_MPU_CPU0_INST,
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cpu_context_offset);
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}
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}
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/*
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* Store the CPU cluster state for L2X0 low power operations.
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*/
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static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
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if (pm_info->l2x0_sar_addr)
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writel_relaxed(save_state, pm_info->l2x0_sar_addr);
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}
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/*
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* Save the L2X0 AUXCTRL and POR value to SAR memory. Its used to
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* in every restore MPUSS OFF path.
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*/
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#ifdef CONFIG_CACHE_L2X0
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static void __init save_l2x0_context(void)
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{
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void __iomem *l2x0_base = omap4_get_l2cache_base();
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if (l2x0_base && sar_base) {
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writel_relaxed(l2x0_saved_regs.aux_ctrl,
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sar_base + L2X0_AUXCTRL_OFFSET);
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writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
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sar_base + L2X0_PREFETCH_CTRL_OFFSET);
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}
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}
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#else
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static void __init save_l2x0_context(void)
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{}
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#endif
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/**
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* omap4_enter_lowpower: OMAP4 MPUSS Low Power Entry Function
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* The purpose of this function is to manage low power programming
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* of OMAP4 MPUSS subsystem
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* @cpu : CPU ID
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* @power_state: Low power state.
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*
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* MPUSS states for the context save:
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* save_state =
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* 0 - Nothing lost and no need to save: MPUSS INACTIVE
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* 1 - CPUx L1 and logic lost: MPUSS CSWR
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* 2 - CPUx L1 and logic lost + GIC lost: MPUSS OSWR
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* 3 - CPUx L1 and logic lost + GIC + L2 lost: DEVICE OFF
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*/
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int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
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unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
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unsigned int wakeup_cpu;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return -ENXIO;
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switch (power_state) {
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case PWRDM_POWER_ON:
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case PWRDM_POWER_INACTIVE:
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save_state = 0;
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break;
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case PWRDM_POWER_OFF:
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cpu_logic_state = PWRDM_POWER_OFF;
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save_state = 1;
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break;
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case PWRDM_POWER_RET:
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if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE))
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save_state = 0;
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break;
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default:
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/*
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* CPUx CSWR is invalid hardware state. Also CPUx OSWR
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* doesn't make much scense, since logic is lost and $L1
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* needs to be cleaned because of coherency. This makes
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* CPUx OSWR equivalent to CPUX OFF and hence not supported
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*/
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WARN_ON(1);
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return -ENXIO;
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}
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pwrdm_pre_transition(NULL);
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/*
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* Check MPUSS next state and save interrupt controller if needed.
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* In MPUSS OSWR or device OFF, interrupt controller contest is lost.
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*/
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mpuss_clear_prev_logic_pwrst();
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if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) &&
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(pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF))
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save_state = 2;
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cpu_clear_prev_logic_pwrst(cpu);
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pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
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pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
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set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
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omap_pm_ops.scu_prepare(cpu, power_state);
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l2x0_pwrst_prepare(cpu, save_state);
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/*
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* Call low level function with targeted low power state.
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*/
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if (save_state)
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cpu_suspend(save_state, omap_pm_ops.finish_suspend);
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else
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omap_pm_ops.finish_suspend(save_state);
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if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu)
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gic_dist_enable();
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/*
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* Restore the CPUx power state to ON otherwise CPUx
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* power domain can transitions to programmed low power
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* state while doing WFI outside the low powe code. On
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* secure devices, CPUx does WFI which can result in
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* domain transition
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*/
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wakeup_cpu = smp_processor_id();
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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pwrdm_post_transition(NULL);
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return 0;
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}
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/**
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* omap4_hotplug_cpu: OMAP4 CPU hotplug entry
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* @cpu : CPU ID
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* @power_state: CPU low power state.
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*/
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int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
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{
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struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
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unsigned int cpu_state = 0;
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if (omap_rev() == OMAP4430_REV_ES1_0)
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return -ENXIO;
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/* Use the achievable power state for the domain */
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power_state = pwrdm_get_valid_lp_state(pm_info->pwrdm,
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false, power_state);
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if (power_state == PWRDM_POWER_OFF)
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cpu_state = 1;
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pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
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pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
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set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.hotplug_restart));
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omap_pm_ops.scu_prepare(cpu, power_state);
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/*
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* CPU never retuns back if targeted power state is OFF mode.
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* CPU ONLINE follows normal CPU ONLINE ptah via
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* omap4_secondary_startup().
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*/
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omap_pm_ops.finish_suspend(cpu_state);
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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return 0;
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}
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/*
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* Enable Mercury Fast HG retention mode by default.
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*/
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static void enable_mercury_retention_mode(void)
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{
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u32 reg;
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reg = omap4_prcm_mpu_read_inst_reg(OMAP54XX_PRCM_MPU_DEVICE_INST,
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OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
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/* Enable HG_EN, HG_RAMPUP = fast mode */
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reg |= BIT(24) | BIT(25);
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omap4_prcm_mpu_write_inst_reg(reg, OMAP54XX_PRCM_MPU_DEVICE_INST,
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OMAP54XX_PRCM_MPU_PRM_PSCON_COUNT_OFFSET);
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}
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/*
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* Initialise OMAP4 MPUSS
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*/
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int __init omap4_mpuss_init(void)
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{
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struct omap4_cpu_pm_info *pm_info;
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if (omap_rev() == OMAP4430_REV_ES1_0) {
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WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
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return -ENODEV;
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}
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/* Initilaise per CPU PM information */
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pm_info = &per_cpu(omap4_pm_info, 0x0);
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if (sar_base) {
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pm_info->scu_sar_addr = sar_base + SCU_OFFSET0;
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if (cpu_is_omap44xx())
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pm_info->wkup_sar_addr = sar_base +
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CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
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else
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pm_info->wkup_sar_addr = sar_base +
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OMAP5_CPU0_WAKEUP_NS_PA_ADDR_OFFSET;
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pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET0;
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}
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pm_info->pwrdm = pwrdm_lookup("cpu0_pwrdm");
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if (!pm_info->pwrdm) {
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pr_err("Lookup failed for CPU0 pwrdm\n");
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return -ENODEV;
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}
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/* Clear CPU previous power domain state */
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pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
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cpu_clear_prev_logic_pwrst(0);
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/* Initialise CPU0 power domain state to ON */
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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pm_info = &per_cpu(omap4_pm_info, 0x1);
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if (sar_base) {
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pm_info->scu_sar_addr = sar_base + SCU_OFFSET1;
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if (cpu_is_omap44xx())
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pm_info->wkup_sar_addr = sar_base +
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CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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else
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pm_info->wkup_sar_addr = sar_base +
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OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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pm_info->l2x0_sar_addr = sar_base + L2X0_SAVE_OFFSET1;
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}
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pm_info->pwrdm = pwrdm_lookup("cpu1_pwrdm");
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if (!pm_info->pwrdm) {
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pr_err("Lookup failed for CPU1 pwrdm\n");
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return -ENODEV;
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}
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/* Clear CPU previous power domain state */
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pwrdm_clear_all_prev_pwrst(pm_info->pwrdm);
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cpu_clear_prev_logic_pwrst(1);
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/* Initialise CPU1 power domain state to ON */
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pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
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mpuss_pd = pwrdm_lookup("mpu_pwrdm");
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if (!mpuss_pd) {
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pr_err("Failed to lookup MPUSS power domain\n");
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return -ENODEV;
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}
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pwrdm_clear_all_prev_pwrst(mpuss_pd);
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mpuss_clear_prev_logic_pwrst();
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if (sar_base) {
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/* Save device type on scratchpad for low level code to use */
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writel_relaxed((omap_type() != OMAP2_DEVICE_TYPE_GP) ? 1 : 0,
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sar_base + OMAP_TYPE_OFFSET);
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save_l2x0_context();
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}
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if (cpu_is_omap44xx()) {
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omap_pm_ops.finish_suspend = omap4_finish_suspend;
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omap_pm_ops.resume = omap4_cpu_resume;
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omap_pm_ops.scu_prepare = scu_pwrst_prepare;
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omap_pm_ops.hotplug_restart = omap4_secondary_startup;
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cpu_context_offset = OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET;
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} else if (soc_is_omap54xx() || soc_is_dra7xx()) {
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cpu_context_offset = OMAP54XX_RM_CPU0_CPU0_CONTEXT_OFFSET;
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enable_mercury_retention_mode();
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}
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if (cpu_is_omap446x())
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omap_pm_ops.hotplug_restart = omap4460_secondary_startup;
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return 0;
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}
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#endif
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u32 omap4_get_cpu1_ns_pa_addr(void)
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{
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return old_cpu1_ns_pa_addr;
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}
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/*
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* For kexec, we must set CPU1_WAKEUP_NS_PA_ADDR to point to
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* current kernel's secondary_startup() early before
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* clockdomains_init(). Otherwise clockdomain_init() can
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* wake CPU1 and cause a hang.
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*/
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void __init omap4_mpuss_early_init(void)
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{
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unsigned long startup_pa;
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void __iomem *ns_pa_addr;
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if (!(soc_is_omap44xx() || soc_is_omap54xx()))
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return;
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sar_base = omap4_get_sar_ram_base();
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/* Save old NS_PA_ADDR for validity checks later on */
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if (soc_is_omap44xx())
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ns_pa_addr = sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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else
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ns_pa_addr = sar_base + OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET;
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old_cpu1_ns_pa_addr = readl_relaxed(ns_pa_addr);
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if (soc_is_omap443x())
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startup_pa = __pa_symbol(omap4_secondary_startup);
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else if (soc_is_omap446x())
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startup_pa = __pa_symbol(omap4460_secondary_startup);
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else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
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startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
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else
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startup_pa = __pa_symbol(omap5_secondary_startup);
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if (soc_is_omap44xx())
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writel_relaxed(startup_pa, sar_base +
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CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
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else
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writel_relaxed(startup_pa, sar_base +
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OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
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}
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