360 lines
12 KiB
C
360 lines
12 KiB
C
/*
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* r8a7790 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#include <mach/r8a7790.h>
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/*
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* MD EXTAL PLL0 PLL1 PLL3
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* 14 13 19 (MHz) *1 *1
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*---------------------------------------------------
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* 0 0 0 15 x 1 x172/2 x208/2 x106
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* 0 0 1 15 x 1 x172/2 x208/2 x88
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* 0 1 0 20 x 1 x130/2 x156/2 x80
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* 0 1 1 20 x 1 x130/2 x156/2 x66
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* 1 0 0 26 / 2 x200/2 x240/2 x122
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* 1 0 1 26 / 2 x200/2 x240/2 x102
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* 1 1 0 30 / 2 x172/2 x208/2 x106
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* 1 1 1 30 / 2 x172/2 x208/2 x88
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*
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* *1 : Table 7.6 indicates VCO ouput (PLLx = VCO/2)
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* see "p1 / 2" on R8A7790_CLOCK_ROOT() below
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*/
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#define CPG_BASE 0xe6150000
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#define CPG_LEN 0x1000
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#define SMSTPCR1 0xe6150134
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#define SMSTPCR2 0xe6150138
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR5 0xe6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xe6150990
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#define SMSTPCR9 0xe6150994
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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#define SD3CKCR 0xE615007C
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#define MMC0CKCR 0xE6150240
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#define MMC1CKCR 0xE6150244
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#define SSPCKCR 0xE6150248
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#define SSPRSCKCR 0xE615024C
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static struct clk_mapping cpg_mapping = {
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.phys = CPG_BASE,
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.len = CPG_LEN,
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};
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static struct clk extal_clk = {
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/* .rate will be updated on r8a7790_clock_init() */
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.mapping = &cpg_mapping,
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};
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static struct sh_clk_ops followparent_clk_ops = {
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.recalc = followparent_recalc,
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};
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static struct clk main_clk = {
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/* .parent will be set r8a73a4_clock_init */
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.ops = &followparent_clk_ops,
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7790_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(lb_clk, pll1_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
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/* fixed ratio clock */
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SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(cp_clk, extal_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(pll1_div2_clk, pll1_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(zg_clk, pll1_clk, 1, 3);
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SH_FIXED_RATIO_CLK_SET(zx_clk, pll1_clk, 1, 3);
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SH_FIXED_RATIO_CLK_SET(zs_clk, pll1_clk, 1, 6);
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SH_FIXED_RATIO_CLK_SET(hp_clk, pll1_clk, 1, 12);
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SH_FIXED_RATIO_CLK_SET(i_clk, pll1_clk, 1, 2);
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SH_FIXED_RATIO_CLK_SET(b_clk, pll1_clk, 1, 12);
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SH_FIXED_RATIO_CLK_SET(p_clk, pll1_clk, 1, 24);
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SH_FIXED_RATIO_CLK_SET(cl_clk, pll1_clk, 1, 48);
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SH_FIXED_RATIO_CLK_SET(m2_clk, pll1_clk, 1, 8);
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SH_FIXED_RATIO_CLK_SET(imp_clk, pll1_clk, 1, 4);
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SH_FIXED_RATIO_CLK_SET(rclk_clk, pll1_clk, 1, (48 * 1024));
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SH_FIXED_RATIO_CLK_SET(oscclk_clk, pll1_clk, 1, (12 * 1024));
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SH_FIXED_RATIO_CLK_SET(zb3_clk, pll3_clk, 1, 4);
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SH_FIXED_RATIO_CLK_SET(zb3d2_clk, pll3_clk, 1, 8);
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SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
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SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
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static struct clk *main_clks[] = {
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&extal_clk,
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&extal_div2_clk,
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&main_clk,
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&pll1_clk,
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&pll1_div2_clk,
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&pll3_clk,
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&lb_clk,
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&qspi_clk,
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&zg_clk,
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&zx_clk,
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&zs_clk,
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&hp_clk,
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&i_clk,
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&b_clk,
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&p_clk,
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&cl_clk,
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&m2_clk,
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&imp_clk,
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&rclk_clk,
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&oscclk_clk,
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&zb3_clk,
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&zb3d2_clk,
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&ddr_clk,
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&mp_clk,
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&cp_clk,
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};
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/* SDHI (DIV4) clock */
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum {
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DIV4_SDH, DIV4_SD0, DIV4_SD1, DIV4_NR
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};
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
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[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
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[DIV4_SD1] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 0, 0x1de0, CLK_ENABLE_ON_INIT),
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};
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/* DIV6 clocks */
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enum {
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DIV6_SD2, DIV6_SD3,
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DIV6_MMC0, DIV6_MMC1,
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DIV6_SSP, DIV6_SSPRS,
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DIV6_NR
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};
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
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[DIV6_SD3] = SH_CLK_DIV6(&pll1_div2_clk, SD3CKCR, 0),
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[DIV6_MMC0] = SH_CLK_DIV6(&pll1_div2_clk, MMC0CKCR, 0),
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[DIV6_MMC1] = SH_CLK_DIV6(&pll1_div2_clk, MMC1CKCR, 0),
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[DIV6_SSP] = SH_CLK_DIV6(&pll1_div2_clk, SSPCKCR, 0),
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[DIV6_SSPRS] = SH_CLK_DIV6(&pll1_div2_clk, SSPRSCKCR, 0),
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};
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/* MSTP */
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enum {
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MSTP931, MSTP930, MSTP929, MSTP928,
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MSTP813,
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MSTP726, MSTP725, MSTP724, MSTP723, MSTP722, MSTP721, MSTP720,
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MSTP717, MSTP716,
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MSTP522,
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MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
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MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
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MSTP124,
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MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP931] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 31, 0), /* I2C0 */
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[MSTP930] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 30, 0), /* I2C1 */
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[MSTP929] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 29, 0), /* I2C2 */
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[MSTP928] = SH_CLK_MSTP32(&hp_clk, SMSTPCR9, 28, 0), /* I2C3 */
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[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
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[MSTP726] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 26, 0), /* LVDS0 */
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[MSTP725] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 25, 0), /* LVDS1 */
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[MSTP724] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 24, 0), /* DU0 */
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[MSTP723] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 23, 0), /* DU1 */
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[MSTP722] = SH_CLK_MSTP32(&zx_clk, SMSTPCR7, 22, 0), /* DU2 */
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[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
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[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
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[MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
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[MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
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[MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
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[MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
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[MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
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[MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SD2], SMSTPCR3, 12, 0), /* SDHI2 */
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[MSTP311] = SH_CLK_MSTP32(&div6_clks[DIV6_SD3], SMSTPCR3, 11, 0), /* SDHI3 */
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[MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1], SMSTPCR3, 5, 0), /* MMC1 */
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[MSTP304] = SH_CLK_MSTP32(&cp_clk, SMSTPCR3, 4, 0), /* TPU0 */
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[MSTP216] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 16, 0), /* SCIFB2 */
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[MSTP207] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 7, 0), /* SCIFB1 */
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[MSTP206] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 6, 0), /* SCIFB0 */
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[MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
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[MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
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[MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
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[MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
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};
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
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CLKDEV_CON_ID("main", &main_clk),
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CLKDEV_CON_ID("pll1", &pll1_clk),
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CLKDEV_CON_ID("pll1_div2", &pll1_div2_clk),
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CLKDEV_CON_ID("pll3", &pll3_clk),
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CLKDEV_CON_ID("zg", &zg_clk),
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CLKDEV_CON_ID("zx", &zx_clk),
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CLKDEV_CON_ID("zs", &zs_clk),
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CLKDEV_CON_ID("hp", &hp_clk),
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CLKDEV_CON_ID("i", &i_clk),
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CLKDEV_CON_ID("b", &b_clk),
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CLKDEV_CON_ID("lb", &lb_clk),
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CLKDEV_CON_ID("p", &p_clk),
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CLKDEV_CON_ID("cl", &cl_clk),
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CLKDEV_CON_ID("m2", &m2_clk),
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CLKDEV_CON_ID("imp", &imp_clk),
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CLKDEV_CON_ID("rclk", &rclk_clk),
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CLKDEV_CON_ID("oscclk", &oscclk_clk),
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CLKDEV_CON_ID("zb3", &zb3_clk),
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CLKDEV_CON_ID("zb3d2", &zb3d2_clk),
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CLKDEV_CON_ID("ddr", &ddr_clk),
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CLKDEV_CON_ID("mp", &mp_clk),
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CLKDEV_CON_ID("qspi", &qspi_clk),
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CLKDEV_CON_ID("cp", &cp_clk),
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/* DIV4 */
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CLKDEV_CON_ID("sdh", &div4_clks[DIV4_SDH]),
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/* DIV6 */
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CLKDEV_CON_ID("ssp", &div6_clks[DIV6_SSP]),
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CLKDEV_CON_ID("ssprs", &div6_clks[DIV6_SSPRS]),
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/* MSTP */
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CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
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CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
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CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
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CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
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CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP206]),
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP207]),
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP202]),
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CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP721]),
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
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CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
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CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
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CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
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CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
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CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
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CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
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CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
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CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("ee160000.sdhi", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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};
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#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
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extal_clk.rate = e * 1000 * 1000; \
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main_clk.parent = m; \
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SH_CLK_SET_RATIO(&pll1_clk_ratio, p1 / 2, 1); \
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if (mode & MD(19)) \
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SH_CLK_SET_RATIO(&pll3_clk_ratio, p31, 1); \
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else \
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SH_CLK_SET_RATIO(&pll3_clk_ratio, p30, 1)
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void __init r8a7790_clock_init(void)
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{
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u32 mode = rcar_gen2_read_mode_pins();
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int k, ret = 0;
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
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break;
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case MD(13):
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R8A7790_CLOCK_ROOT(20, &extal_clk, 130, 156, 80, 66);
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break;
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case MD(14):
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R8A7790_CLOCK_ROOT(26, &extal_div2_clk, 200, 240, 122, 102);
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break;
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case MD(13) | MD(14):
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R8A7790_CLOCK_ROOT(30, &extal_div2_clk, 172, 208, 106, 88);
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break;
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}
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if (mode & (MD(18)))
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SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 36);
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else
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SH_CLK_SET_RATIO(&lb_clk_ratio, 1, 24);
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if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
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SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
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else
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SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
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for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
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ret = clk_register(main_clks[k]);
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if (!ret)
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ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
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clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
if (!ret)
|
|
shmobile_clk_init();
|
|
else
|
|
panic("failed to setup r8a7790 clocks\n");
|
|
}
|