273 lines
6.4 KiB
C
273 lines
6.4 KiB
C
/*
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* Marvell EBU SoC Device Bus Controller
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* (memory controller for NOR/NAND/SRAM/FPGA devices)
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*
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* Copyright (C) 2013 Marvell
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/mbus.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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/* Register definitions */
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#define DEV_WIDTH_BIT 30
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#define BADR_SKEW_BIT 28
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#define RD_HOLD_BIT 23
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#define ACC_NEXT_BIT 17
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#define RD_SETUP_BIT 12
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#define ACC_FIRST_BIT 6
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#define SYNC_ENABLE_BIT 24
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#define WR_HIGH_BIT 16
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#define WR_LOW_BIT 8
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#define READ_PARAM_OFFSET 0x0
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#define WRITE_PARAM_OFFSET 0x4
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struct devbus_read_params {
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u32 bus_width;
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u32 badr_skew;
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u32 turn_off;
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u32 acc_first;
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u32 acc_next;
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u32 rd_setup;
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u32 rd_hold;
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};
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struct devbus_write_params {
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u32 sync_enable;
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u32 wr_high;
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u32 wr_low;
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u32 ale_wr;
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};
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struct devbus {
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struct device *dev;
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void __iomem *base;
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unsigned long tick_ps;
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};
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static int get_timing_param_ps(struct devbus *devbus,
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struct device_node *node,
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const char *name,
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u32 *ticks)
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{
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u32 time_ps;
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int err;
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err = of_property_read_u32(node, name, &time_ps);
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if (err < 0) {
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dev_err(devbus->dev, "%s has no '%s' property\n",
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name, node->full_name);
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return err;
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}
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*ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
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dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
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name, time_ps, *ticks);
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return 0;
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}
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static int devbus_set_timing_params(struct devbus *devbus,
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struct device_node *node)
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{
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struct devbus_read_params r;
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struct devbus_write_params w;
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u32 value;
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int err;
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dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
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devbus->tick_ps);
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/* Get read timings */
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err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
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if (err < 0) {
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dev_err(devbus->dev,
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"%s has no 'devbus,bus-width' property\n",
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node->full_name);
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return err;
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}
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/* Convert bit width to byte width */
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r.bus_width /= 8;
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err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
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&r.badr_skew);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
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&r.turn_off);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
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&r.acc_first);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
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&r.acc_next);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
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&r.rd_setup);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
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&r.rd_hold);
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if (err < 0)
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return err;
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/* Get write timings */
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err = of_property_read_u32(node, "devbus,sync-enable",
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&w.sync_enable);
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if (err < 0) {
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dev_err(devbus->dev,
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"%s has no 'devbus,sync-enable' property\n",
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node->full_name);
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return err;
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}
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err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
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&w.ale_wr);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
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&w.wr_low);
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if (err < 0)
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return err;
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err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
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&w.wr_high);
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if (err < 0)
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return err;
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/* Set read timings */
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value = r.bus_width << DEV_WIDTH_BIT |
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r.badr_skew << BADR_SKEW_BIT |
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r.rd_hold << RD_HOLD_BIT |
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r.acc_next << ACC_NEXT_BIT |
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r.rd_setup << RD_SETUP_BIT |
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r.acc_first << ACC_FIRST_BIT |
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r.turn_off;
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dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
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devbus->base + READ_PARAM_OFFSET,
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value);
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writel(value, devbus->base + READ_PARAM_OFFSET);
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/* Set write timings */
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value = w.sync_enable << SYNC_ENABLE_BIT |
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w.wr_low << WR_LOW_BIT |
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w.wr_high << WR_HIGH_BIT |
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w.ale_wr;
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dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
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devbus->base + WRITE_PARAM_OFFSET,
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value);
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writel(value, devbus->base + WRITE_PARAM_OFFSET);
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return 0;
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}
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static int mvebu_devbus_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *node = pdev->dev.of_node;
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struct devbus *devbus;
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struct resource *res;
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struct clk *clk;
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unsigned long rate;
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int err;
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devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
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if (!devbus)
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return -ENOMEM;
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devbus->dev = dev;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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devbus->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(devbus->base))
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return PTR_ERR(devbus->base);
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clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk))
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return PTR_ERR(clk);
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clk_prepare_enable(clk);
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/*
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* Obtain clock period in picoseconds,
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* we need this in order to convert timing
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* parameters from cycles to picoseconds.
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*/
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rate = clk_get_rate(clk) / 1000;
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devbus->tick_ps = 1000000000 / rate;
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/* Read the device tree node and set the new timing parameters */
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err = devbus_set_timing_params(devbus, node);
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if (err < 0)
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return err;
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/*
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* We need to create a child device explicitly from here to
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* guarantee that the child will be probed after the timing
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* parameters for the bus are written.
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*/
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err = of_platform_populate(node, NULL, NULL, dev);
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if (err < 0)
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return err;
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return 0;
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}
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static const struct of_device_id mvebu_devbus_of_match[] = {
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{ .compatible = "marvell,mvebu-devbus" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
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static struct platform_driver mvebu_devbus_driver = {
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.probe = mvebu_devbus_probe,
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.driver = {
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.name = "mvebu-devbus",
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.owner = THIS_MODULE,
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.of_match_table = mvebu_devbus_of_match,
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},
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};
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static int __init mvebu_devbus_init(void)
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{
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return platform_driver_register(&mvebu_devbus_driver);
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}
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module_init(mvebu_devbus_init);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
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MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");
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