302 lines
7.9 KiB
C
302 lines
7.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-sc7180.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "gdsc.h"
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#define CX_GMU_CBCR_SLEEP_MASK 0xF
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#define CX_GMU_CBCR_SLEEP_SHIFT 4
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#define CX_GMU_CBCR_WAKE_MASK 0xF
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#define CX_GMU_CBCR_WAKE_SHIFT 8
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#define CLK_DIS_WAIT_SHIFT 12
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#define CLK_DIS_WAIT_MASK (0xf << CLK_DIS_WAIT_SHIFT)
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enum {
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P_BI_TCXO,
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P_CORE_BI_PLL_TEST_SE,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL1_OUT_EVEN,
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P_GPU_CC_PLL1_OUT_MAIN,
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P_GPU_CC_PLL1_OUT_ODD,
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};
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static const struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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static struct clk_alpha_pll gpu_cc_pll1 = {
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.offset = 0x100,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL1_OUT_MAIN, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &gpu_cc_pll1.clkr.hw },
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{ .fw_name = "gcc_gpu_gpll0_clk_src" },
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{ .fw_name = "gcc_gpu_gpll0_div_clk_src" },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_data = &(const struct clk_parent_data){
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.hw = &gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc cx_gdsc = {
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.gdscr = 0x106c,
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.gds_hw_ctrl = 0x1540,
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.pd = {
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.name = "cx_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = VOTABLE,
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};
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/*
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* On SC7180 the GPU GX domain is *almost* entirely controlled by the GMU
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* running in the CX domain so the CPU doesn't need to know anything about the
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* GX domain EXCEPT....
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*
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* Hardware constraints dictate that the GX be powered down before the CX. If
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* the GMU crashes it could leave the GX on. In order to successfully bring back
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* the device the CPU needs to disable the GX headswitch. There being no sane
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* way to reach in and touch that register from deep inside the GPU driver we
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* need to set up the infrastructure to be able to ensure that the GPU can
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* ensure that the GX is off during this super special case. We do this by
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* defining a GX gdsc with a dummy enable function and a "default" disable
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* function.
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*
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* This allows us to attach with genpd_dev_pm_attach_by_name() in the GPU
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* driver. During power up, nothing will happen from the CPU (and the GMU will
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* power up normally but during power down this will ensure that the GX domain
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* is *really* off - this gives us a semi standard way of doing what we need.
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*/
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static int gx_gdsc_enable(struct generic_pm_domain *domain)
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{
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/* Do nothing but give genpd the impression that we were successful */
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return 0;
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}
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static struct gdsc gx_gdsc = {
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.gdscr = 0x100c,
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.clamp_io_ctrl = 0x1508,
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.pd = {
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.name = "gx_gdsc",
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.power_on = gx_gdsc_enable,
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = CLAMP_IO,
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};
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static struct gdsc *gpu_cc_sc7180_gdscs[] = {
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[CX_GDSC] = &cx_gdsc,
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[GX_GDSC] = &gx_gdsc,
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};
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static struct clk_regmap *gpu_cc_sc7180_clocks[] = {
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_PLL1] = &gpu_cc_pll1.clkr,
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};
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static const struct regmap_config gpu_cc_sc7180_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x8008,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpu_cc_sc7180_desc = {
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.config = &gpu_cc_sc7180_regmap_config,
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.clks = gpu_cc_sc7180_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_sc7180_clocks),
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.gdscs = gpu_cc_sc7180_gdscs,
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.num_gdscs = ARRAY_SIZE(gpu_cc_sc7180_gdscs),
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};
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static const struct of_device_id gpu_cc_sc7180_match_table[] = {
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{ .compatible = "qcom,sc7180-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_sc7180_match_table);
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static int gpu_cc_sc7180_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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struct alpha_pll_config gpu_cc_pll_config = {};
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unsigned int value, mask;
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regmap = qcom_cc_map(pdev, &gpu_cc_sc7180_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/* 360MHz Configuration */
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gpu_cc_pll_config.l = 0x12;
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gpu_cc_pll_config.alpha = 0xc000;
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gpu_cc_pll_config.config_ctl_val = 0x20485699;
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gpu_cc_pll_config.config_ctl_hi_val = 0x00002067;
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gpu_cc_pll_config.user_ctl_val = 0x00000001;
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gpu_cc_pll_config.user_ctl_hi_val = 0x00004805;
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gpu_cc_pll_config.test_ctl_hi_val = 0x40000000;
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clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll_config);
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/* Recommended WAKEUP/SLEEP settings for the gpu_cc_cx_gmu_clk */
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mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
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mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
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value = 0xF << CX_GMU_CBCR_WAKE_SHIFT | 0xF << CX_GMU_CBCR_SLEEP_SHIFT;
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regmap_update_bits(regmap, 0x1098, mask, value);
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/* Configure clk_dis_wait for gpu_cx_gdsc */
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regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
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8 << CLK_DIS_WAIT_SHIFT);
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return qcom_cc_really_probe(pdev, &gpu_cc_sc7180_desc, regmap);
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}
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static struct platform_driver gpu_cc_sc7180_driver = {
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.probe = gpu_cc_sc7180_probe,
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.driver = {
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.name = "sc7180-gpucc",
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.of_match_table = gpu_cc_sc7180_match_table,
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},
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};
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static int __init gpu_cc_sc7180_init(void)
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{
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return platform_driver_register(&gpu_cc_sc7180_driver);
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}
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subsys_initcall(gpu_cc_sc7180_init);
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static void __exit gpu_cc_sc7180_exit(void)
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{
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platform_driver_unregister(&gpu_cc_sc7180_driver);
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}
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module_exit(gpu_cc_sc7180_exit);
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MODULE_DESCRIPTION("QTI GPU_CC SC7180 Driver");
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MODULE_LICENSE("GPL v2");
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