200 lines
6.3 KiB
Plaintext
200 lines
6.3 KiB
Plaintext
FPGA Manager Core
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Alan Tull 2015
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Overview
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========
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The FPGA manager core exports a set of functions for programming an FPGA with
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an image. The API is manufacturer agnostic. All manufacturer specifics are
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hidden away in a low level driver which registers a set of ops with the core.
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The FPGA image data itself is very manufacturer specific, but for our purposes
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it's just binary data. The FPGA manager core won't parse it.
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API Functions:
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==============
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To program the FPGA from a file or from a buffer:
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-------------------------------------------------
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int fpga_mgr_buf_load(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *buf, size_t count);
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Load the FPGA from an image which exists as a contiguous buffer in
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memory. Allocating contiguous kernel memory for the buffer should be avoided,
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users are encouraged to use the _sg interface instead of this.
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int fpga_mgr_buf_load_sg(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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struct sg_table *sgt);
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Load the FPGA from an image from non-contiguous in memory. Callers can
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construct a sg_table using alloc_page backed memory.
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int fpga_mgr_firmware_load(struct fpga_manager *mgr,
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struct fpga_image_info *info,
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const char *image_name);
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Load the FPGA from an image which exists as a file. The image file must be on
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the firmware search path (see the firmware class documentation). If successful,
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the FPGA ends up in operating mode. Return 0 on success or a negative error
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code.
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A FPGA design contained in a FPGA image file will likely have particulars that
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affect how the image is programmed to the FPGA. These are contained in struct
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fpga_image_info. Currently the only such particular is a single flag bit
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indicating whether the image is for full or partial reconfiguration.
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To get/put a reference to a FPGA manager:
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-----------------------------------------
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struct fpga_manager *of_fpga_mgr_get(struct device_node *node);
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struct fpga_manager *fpga_mgr_get(struct device *dev);
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Given a DT node or device, get an exclusive reference to a FPGA manager.
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void fpga_mgr_put(struct fpga_manager *mgr);
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Release the reference.
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To register or unregister the low level FPGA-specific driver:
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-------------------------------------------------------------
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int fpga_mgr_register(struct device *dev, const char *name,
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const struct fpga_manager_ops *mops,
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void *priv);
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void fpga_mgr_unregister(struct device *dev);
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Use of these two functions is described below in "How To Support a new FPGA
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device."
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How to write an image buffer to a supported FPGA
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================================================
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/* Include to get the API */
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#include <linux/fpga/fpga-mgr.h>
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/* device node that specifies the FPGA manager to use */
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struct device_node *mgr_node = ...
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/* FPGA image is in this buffer. count is size of the buffer. */
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char *buf = ...
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int count = ...
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/* struct with information about the FPGA image to program. */
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struct fpga_image_info info;
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/* flags indicates whether to do full or partial reconfiguration */
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info.flags = 0;
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int ret;
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/* Get exclusive control of FPGA manager */
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struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node);
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/* Load the buffer to the FPGA */
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ret = fpga_mgr_buf_load(mgr, &info, buf, count);
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/* Release the FPGA manager */
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fpga_mgr_put(mgr);
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How to write an image file to a supported FPGA
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==============================================
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/* Include to get the API */
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#include <linux/fpga/fpga-mgr.h>
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/* device node that specifies the FPGA manager to use */
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struct device_node *mgr_node = ...
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/* FPGA image is in this file which is in the firmware search path */
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const char *path = "fpga-image-9.rbf"
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/* struct with information about the FPGA image to program. */
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struct fpga_image_info info;
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/* flags indicates whether to do full or partial reconfiguration */
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info.flags = 0;
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int ret;
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/* Get exclusive control of FPGA manager */
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struct fpga_manager *mgr = of_fpga_mgr_get(mgr_node);
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/* Get the firmware image (path) and load it to the FPGA */
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ret = fpga_mgr_firmware_load(mgr, &info, path);
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/* Release the FPGA manager */
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fpga_mgr_put(mgr);
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How to support a new FPGA device
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================================
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To add another FPGA manager, write a driver that implements a set of ops. The
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probe function calls fpga_mgr_register(), such as:
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static const struct fpga_manager_ops socfpga_fpga_ops = {
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.write_init = socfpga_fpga_ops_configure_init,
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.write = socfpga_fpga_ops_configure_write,
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.write_complete = socfpga_fpga_ops_configure_complete,
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.state = socfpga_fpga_ops_state,
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};
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static int socfpga_fpga_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct socfpga_fpga_priv *priv;
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int ret;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* ... do ioremaps, get interrupts, etc. and save
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them in priv... */
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return fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
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&socfpga_fpga_ops, priv);
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}
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static int socfpga_fpga_remove(struct platform_device *pdev)
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{
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fpga_mgr_unregister(&pdev->dev);
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return 0;
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}
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The ops will implement whatever device specific register writes are needed to
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do the programming sequence for this particular FPGA. These ops return 0 for
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success or negative error codes otherwise.
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The programming sequence is:
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1. .write_init
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2. .write or .write_sg (may be called once or multiple times)
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3. .write_complete
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The .write_init function will prepare the FPGA to receive the image data. The
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buffer passed into .write_init will be atmost .initial_header_size bytes long,
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if the whole bitstream is not immediately available then the core code will
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buffer up at least this much before starting.
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The .write function writes a buffer to the FPGA. The buffer may be contain the
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whole FPGA image or may be a smaller chunk of an FPGA image. In the latter
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case, this function is called multiple times for successive chunks. This interface
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is suitable for drivers which use PIO.
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The .write_sg version behaves the same as .write except the input is a sg_table
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scatter list. This interface is suitable for drivers which use DMA.
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The .write_complete function is called after all the image has been written
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to put the FPGA into operating mode.
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The ops include a .state function which will read the hardware FPGA manager and
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return a code of type enum fpga_mgr_states. It doesn't result in a change in
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hardware state.
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