309 lines
9.1 KiB
C
309 lines
9.1 KiB
C
/* sc520cdp.c -- MTD map driver for AMD SC520 Customer Development Platform
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*
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* Copyright (C) 2001 Sysgo Real-Time Solutions GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*
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*
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* The SC520CDP is an evaluation board for the Elan SC520 processor available
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* from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
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* and up to 512 KiB of 8-bit DIL Flash ROM.
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* For details see http://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/map.h>
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#include <linux/mtd/concat.h>
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/*
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** The Embedded Systems BIOS decodes the first FLASH starting at
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** 0x8400000. This is a *terrible* place for it because accessing
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** the flash at this location causes the A22 address line to be high
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** (that's what 0x8400000 binary's ought to be). But this is the highest
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** order address line on the raw flash devices themselves!!
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** This causes the top HALF of the flash to be accessed first. Beyond
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** the physical limits of the flash, the flash chip aliases over (to
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** 0x880000 which causes the bottom half to be accessed. This splits the
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** flash into two and inverts it! If you then try to access this from another
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** program that does NOT do this insanity, then you *will* access the
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** first half of the flash, but not find what you expect there. That
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** stuff is in the *second* half! Similarly, the address used by the
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** BIOS for the second FLASH bank is also quite a bad choice.
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** If REPROGRAM_PAR is defined below (the default), then this driver will
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** choose more useful addresses for the FLASH banks by reprogramming the
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** responsible PARxx registers in the SC520's MMCR region. This will
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** cause the settings to be incompatible with the BIOS's settings, which
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** shouldn't be a problem since you are running Linux, (i.e. the BIOS is
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** not much use anyway). However, if you need to be compatible with
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** the BIOS for some reason, just undefine REPROGRAM_PAR.
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*/
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#define REPROGRAM_PAR
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#ifdef REPROGRAM_PAR
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/* These are the addresses we want.. */
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#define WINDOW_ADDR_0 0x08800000
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#define WINDOW_ADDR_1 0x09000000
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#define WINDOW_ADDR_2 0x09800000
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/* .. and these are the addresses the BIOS gives us */
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#define WINDOW_ADDR_0_BIOS 0x08400000
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#define WINDOW_ADDR_1_BIOS 0x08c00000
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#define WINDOW_ADDR_2_BIOS 0x09400000
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#else
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#define WINDOW_ADDR_0 0x08400000
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#define WINDOW_ADDR_1 0x08C00000
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#define WINDOW_ADDR_2 0x09400000
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#endif
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#define WINDOW_SIZE_0 0x00800000
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#define WINDOW_SIZE_1 0x00800000
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#define WINDOW_SIZE_2 0x00080000
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static struct map_info sc520cdp_map[] = {
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{
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.name = "SC520CDP Flash Bank #0",
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.size = WINDOW_SIZE_0,
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.bankwidth = 4,
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.phys = WINDOW_ADDR_0
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},
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{
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.name = "SC520CDP Flash Bank #1",
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.size = WINDOW_SIZE_1,
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.bankwidth = 4,
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.phys = WINDOW_ADDR_1
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},
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{
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.name = "SC520CDP DIL Flash",
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.size = WINDOW_SIZE_2,
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.bankwidth = 1,
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.phys = WINDOW_ADDR_2
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},
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};
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#define NUM_FLASH_BANKS ARRAY_SIZE(sc520cdp_map)
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static struct mtd_info *mymtd[NUM_FLASH_BANKS];
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static struct mtd_info *merged_mtd;
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#ifdef REPROGRAM_PAR
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/*
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** The SC520 MMCR (memory mapped control register) region resides
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** at 0xFFFEF000. The 16 Programmable Address Region (PAR) registers
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** are at offset 0x88 in the MMCR:
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*/
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#define SC520_MMCR_BASE 0xFFFEF000
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#define SC520_MMCR_EXTENT 0x1000
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#define SC520_PAR(x) ((0x88/sizeof(unsigned long)) + (x))
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#define NUM_SC520_PAR 16 /* total number of PAR registers */
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/*
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** The highest three bits in a PAR register determine what target
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** device is controlled by this PAR. Here, only ROMCS? and BOOTCS
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** devices are of interest.
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*/
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#define SC520_PAR_BOOTCS (0x4<<29)
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#define SC520_PAR_ROMCS0 (0x5<<29)
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#define SC520_PAR_ROMCS1 (0x6<<29)
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#define SC520_PAR_TRGDEV (0x7<<29)
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/*
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** Bits 28 thru 26 determine some attributes for the
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** region controlled by the PAR. (We only use non-cacheable)
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*/
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#define SC520_PAR_WRPROT (1<<26) /* write protected */
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#define SC520_PAR_NOCACHE (1<<27) /* non-cacheable */
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#define SC520_PAR_NOEXEC (1<<28) /* code execution denied */
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/*
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** Bit 25 determines the granularity: 4K or 64K
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*/
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#define SC520_PAR_PG_SIZ4 (0<<25)
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#define SC520_PAR_PG_SIZ64 (1<<25)
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/*
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** Build a value to be written into a PAR register.
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** We only need ROM entries, 64K page size:
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*/
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#define SC520_PAR_ENTRY(trgdev, address, size) \
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((trgdev) | SC520_PAR_NOCACHE | SC520_PAR_PG_SIZ64 | \
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(address) >> 16 | (((size) >> 16) - 1) << 14)
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struct sc520_par_table
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{
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unsigned long trgdev;
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unsigned long new_par;
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unsigned long default_address;
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};
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static const struct sc520_par_table par_table[NUM_FLASH_BANKS] =
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{
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{ /* Flash Bank #0: selected by ROMCS0 */
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SC520_PAR_ROMCS0,
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SC520_PAR_ENTRY(SC520_PAR_ROMCS0, WINDOW_ADDR_0, WINDOW_SIZE_0),
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WINDOW_ADDR_0_BIOS
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},
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{ /* Flash Bank #1: selected by ROMCS1 */
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SC520_PAR_ROMCS1,
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SC520_PAR_ENTRY(SC520_PAR_ROMCS1, WINDOW_ADDR_1, WINDOW_SIZE_1),
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WINDOW_ADDR_1_BIOS
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},
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{ /* DIL (BIOS) Flash: selected by BOOTCS */
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SC520_PAR_BOOTCS,
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SC520_PAR_ENTRY(SC520_PAR_BOOTCS, WINDOW_ADDR_2, WINDOW_SIZE_2),
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WINDOW_ADDR_2_BIOS
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}
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};
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static void sc520cdp_setup_par(void)
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{
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unsigned long __iomem *mmcr;
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unsigned long mmcr_val;
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int i, j;
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/* map in SC520's MMCR area */
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mmcr = ioremap_nocache(SC520_MMCR_BASE, SC520_MMCR_EXTENT);
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if(!mmcr) { /* ioremap_nocache failed: skip the PAR reprogramming */
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/* force physical address fields to BIOS defaults: */
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for(i = 0; i < NUM_FLASH_BANKS; i++)
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sc520cdp_map[i].phys = par_table[i].default_address;
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return;
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}
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/*
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** Find the PARxx registers that are responsible for activating
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** ROMCS0, ROMCS1 and BOOTCS. Reprogram each of these with a
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** new value from the table.
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*/
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for(i = 0; i < NUM_FLASH_BANKS; i++) { /* for each par_table entry */
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for(j = 0; j < NUM_SC520_PAR; j++) { /* for each PAR register */
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mmcr_val = readl(&mmcr[SC520_PAR(j)]);
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/* if target device field matches, reprogram the PAR */
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if((mmcr_val & SC520_PAR_TRGDEV) == par_table[i].trgdev)
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{
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writel(par_table[i].new_par, &mmcr[SC520_PAR(j)]);
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break;
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}
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}
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if(j == NUM_SC520_PAR)
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{ /* no matching PAR found: try default BIOS address */
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printk(KERN_NOTICE "Could not find PAR responsible for %s\n",
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sc520cdp_map[i].name);
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printk(KERN_NOTICE "Trying default address 0x%lx\n",
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par_table[i].default_address);
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sc520cdp_map[i].phys = par_table[i].default_address;
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}
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}
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iounmap(mmcr);
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}
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#endif
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static int __init init_sc520cdp(void)
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{
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int i, j, devices_found = 0;
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#ifdef REPROGRAM_PAR
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/* reprogram PAR registers so flash appears at the desired addresses */
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sc520cdp_setup_par();
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#endif
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for (i = 0; i < NUM_FLASH_BANKS; i++) {
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printk(KERN_NOTICE "SC520 CDP flash device: 0x%Lx at 0x%Lx\n",
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(unsigned long long)sc520cdp_map[i].size,
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(unsigned long long)sc520cdp_map[i].phys);
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sc520cdp_map[i].virt = ioremap_nocache(sc520cdp_map[i].phys, sc520cdp_map[i].size);
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if (!sc520cdp_map[i].virt) {
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printk("Failed to ioremap_nocache\n");
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for (j = 0; j < i; j++) {
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if (mymtd[j]) {
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map_destroy(mymtd[j]);
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iounmap(sc520cdp_map[j].virt);
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}
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}
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return -EIO;
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}
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simple_map_init(&sc520cdp_map[i]);
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mymtd[i] = do_map_probe("cfi_probe", &sc520cdp_map[i]);
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if(!mymtd[i])
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mymtd[i] = do_map_probe("jedec_probe", &sc520cdp_map[i]);
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if(!mymtd[i])
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mymtd[i] = do_map_probe("map_rom", &sc520cdp_map[i]);
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if (mymtd[i]) {
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mymtd[i]->owner = THIS_MODULE;
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++devices_found;
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}
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else {
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iounmap(sc520cdp_map[i].virt);
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}
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}
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if(devices_found >= 2) {
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/* Combine the two flash banks into a single MTD device & register it: */
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merged_mtd = mtd_concat_create(mymtd, 2, "SC520CDP Flash Banks #0 and #1");
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if(merged_mtd)
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mtd_device_register(merged_mtd, NULL, 0);
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}
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if(devices_found == 3) /* register the third (DIL-Flash) device */
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mtd_device_register(mymtd[2], NULL, 0);
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return(devices_found ? 0 : -ENXIO);
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}
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static void __exit cleanup_sc520cdp(void)
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{
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int i;
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if (merged_mtd) {
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mtd_device_unregister(merged_mtd);
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mtd_concat_destroy(merged_mtd);
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}
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if (mymtd[2])
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mtd_device_unregister(mymtd[2]);
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for (i = 0; i < NUM_FLASH_BANKS; i++) {
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if (mymtd[i])
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map_destroy(mymtd[i]);
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if (sc520cdp_map[i].virt) {
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iounmap(sc520cdp_map[i].virt);
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sc520cdp_map[i].virt = NULL;
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}
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}
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}
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module_init(init_sc520cdp);
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module_exit(cleanup_sc520cdp);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Sysgo Real-Time Solutions GmbH");
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MODULE_DESCRIPTION("MTD map driver for AMD SC520 Customer Development Platform");
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