105 lines
3.5 KiB
C
105 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/spinlock.h>
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#include <linux/percpu.h>
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#include <asm/cpu_entry_area.h>
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#include <asm/pgtable.h>
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#include <asm/fixmap.h>
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#include <asm/desc.h>
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static DEFINE_PER_CPU_PAGE_ALIGNED(struct entry_stack_page, entry_stack_storage);
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#ifdef CONFIG_X86_64
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static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
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[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
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#endif
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static void __init
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set_percpu_fixmap_pages(int idx, void *ptr, int pages, pgprot_t prot)
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{
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for ( ; pages; pages--, idx--, ptr += PAGE_SIZE)
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__set_fixmap(idx, per_cpu_ptr_to_phys(ptr), prot);
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}
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/* Setup the fixmap mappings only once per-processor */
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static void __init setup_cpu_entry_area(int cpu)
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{
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#ifdef CONFIG_X86_64
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extern char _entry_trampoline[];
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/* On 64-bit systems, we use a read-only fixmap GDT and TSS. */
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pgprot_t gdt_prot = PAGE_KERNEL_RO;
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pgprot_t tss_prot = PAGE_KERNEL_RO;
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#else
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/*
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* On native 32-bit systems, the GDT cannot be read-only because
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* our double fault handler uses a task gate, and entering through
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* a task gate needs to change an available TSS to busy. If the
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* GDT is read-only, that will triple fault. The TSS cannot be
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* read-only because the CPU writes to it on task switches.
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*
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* On Xen PV, the GDT must be read-only because the hypervisor
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* requires it.
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*/
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pgprot_t gdt_prot = boot_cpu_has(X86_FEATURE_XENPV) ?
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PAGE_KERNEL_RO : PAGE_KERNEL;
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pgprot_t tss_prot = PAGE_KERNEL;
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#endif
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__set_fixmap(get_cpu_entry_area_index(cpu, gdt), get_cpu_gdt_paddr(cpu), gdt_prot);
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set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, entry_stack_page),
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per_cpu_ptr(&entry_stack_storage, cpu), 1,
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PAGE_KERNEL);
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/*
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* The Intel SDM says (Volume 3, 7.2.1):
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*
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* Avoid placing a page boundary in the part of the TSS that the
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* processor reads during a task switch (the first 104 bytes). The
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* processor may not correctly perform address translations if a
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* boundary occurs in this area. During a task switch, the processor
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* reads and writes into the first 104 bytes of each TSS (using
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* contiguous physical addresses beginning with the physical address
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* of the first byte of the TSS). So, after TSS access begins, if
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* part of the 104 bytes is not physically contiguous, the processor
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* will access incorrect information without generating a page-fault
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* exception.
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*
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* There are also a lot of errata involving the TSS spanning a page
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* boundary. Assert that we're not doing that.
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*/
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BUILD_BUG_ON((offsetof(struct tss_struct, x86_tss) ^
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offsetofend(struct tss_struct, x86_tss)) & PAGE_MASK);
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BUILD_BUG_ON(sizeof(struct tss_struct) % PAGE_SIZE != 0);
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set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, tss),
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&per_cpu(cpu_tss_rw, cpu),
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sizeof(struct tss_struct) / PAGE_SIZE,
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tss_prot);
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#ifdef CONFIG_X86_32
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per_cpu(cpu_entry_area, cpu) = get_cpu_entry_area(cpu);
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#endif
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#ifdef CONFIG_X86_64
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BUILD_BUG_ON(sizeof(exception_stacks) % PAGE_SIZE != 0);
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BUILD_BUG_ON(sizeof(exception_stacks) !=
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sizeof(((struct cpu_entry_area *)0)->exception_stacks));
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set_percpu_fixmap_pages(get_cpu_entry_area_index(cpu, exception_stacks),
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&per_cpu(exception_stacks, cpu),
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sizeof(exception_stacks) / PAGE_SIZE,
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PAGE_KERNEL);
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__set_fixmap(get_cpu_entry_area_index(cpu, entry_trampoline),
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__pa_symbol(_entry_trampoline), PAGE_KERNEL_RX);
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#endif
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}
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void __init setup_cpu_entry_areas(void)
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{
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unsigned int cpu;
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for_each_possible_cpu(cpu)
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setup_cpu_entry_area(cpu);
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}
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