240 lines
6.2 KiB
C
240 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* JZ4780 EFUSE Memory Support driver
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*
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* Copyright (c) 2017 PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>
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* Copyright (c) 2020 H. Nikolaus Schaller <hns@goldelico.com>
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*/
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/*
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* Currently supports JZ4780 efuse which has 8K programmable bit.
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* Efuse is separated into seven segments as below:
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*
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* -----------------------------------------------------------------------
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* | 64 bit | 128 bit | 128 bit | 3520 bit | 8 bit | 2296 bit | 2048 bit |
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* -----------------------------------------------------------------------
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*
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* The rom itself is accessed using a 9 bit address line and an 8 word wide bus
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* which reads/writes based on strobes. The strobe is configured in the config
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* register and is based on number of cycles of the bus clock.
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*
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* Driver supports read only as the writes are done in the Factory.
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/nvmem-provider.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/timer.h>
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#define JZ_EFUCTRL (0x0) /* Control Register */
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#define JZ_EFUCFG (0x4) /* Configure Register*/
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#define JZ_EFUSTATE (0x8) /* Status Register */
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#define JZ_EFUDATA(n) (0xC + (n) * 4)
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/* We read 32 byte chunks to avoid complexity in the driver. */
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#define JZ_EFU_READ_SIZE 32
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#define EFUCTRL_ADDR_MASK 0x3FF
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#define EFUCTRL_ADDR_SHIFT 21
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#define EFUCTRL_LEN_MASK 0x1F
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#define EFUCTRL_LEN_SHIFT 16
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#define EFUCTRL_PG_EN BIT(15)
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#define EFUCTRL_WR_EN BIT(1)
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#define EFUCTRL_RD_EN BIT(0)
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#define EFUCFG_INT_EN BIT(31)
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#define EFUCFG_RD_ADJ_MASK 0xF
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#define EFUCFG_RD_ADJ_SHIFT 20
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#define EFUCFG_RD_STR_MASK 0xF
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#define EFUCFG_RD_STR_SHIFT 16
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#define EFUCFG_WR_ADJ_MASK 0xF
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#define EFUCFG_WR_ADJ_SHIFT 12
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#define EFUCFG_WR_STR_MASK 0xFFF
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#define EFUCFG_WR_STR_SHIFT 0
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#define EFUSTATE_WR_DONE BIT(1)
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#define EFUSTATE_RD_DONE BIT(0)
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struct jz4780_efuse {
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struct device *dev;
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struct regmap *map;
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struct clk *clk;
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};
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/* main entry point */
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static int jz4780_efuse_read(void *context, unsigned int offset,
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void *val, size_t bytes)
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{
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struct jz4780_efuse *efuse = context;
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while (bytes > 0) {
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size_t start = offset & ~(JZ_EFU_READ_SIZE - 1);
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size_t chunk = min(bytes, (start + JZ_EFU_READ_SIZE)
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- offset);
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char buf[JZ_EFU_READ_SIZE];
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unsigned int tmp;
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u32 ctrl;
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int ret;
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ctrl = (start << EFUCTRL_ADDR_SHIFT)
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| ((JZ_EFU_READ_SIZE - 1) << EFUCTRL_LEN_SHIFT)
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| EFUCTRL_RD_EN;
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regmap_update_bits(efuse->map, JZ_EFUCTRL,
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(EFUCTRL_ADDR_MASK << EFUCTRL_ADDR_SHIFT) |
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(EFUCTRL_LEN_MASK << EFUCTRL_LEN_SHIFT) |
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EFUCTRL_PG_EN | EFUCTRL_WR_EN |
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EFUCTRL_RD_EN,
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ctrl);
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ret = regmap_read_poll_timeout(efuse->map, JZ_EFUSTATE,
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tmp, tmp & EFUSTATE_RD_DONE,
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1 * MSEC_PER_SEC,
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50 * MSEC_PER_SEC);
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if (ret < 0) {
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dev_err(efuse->dev, "Time out while reading efuse data");
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return ret;
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}
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ret = regmap_bulk_read(efuse->map, JZ_EFUDATA(0),
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buf, JZ_EFU_READ_SIZE / sizeof(u32));
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if (ret < 0)
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return ret;
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memcpy(val, &buf[offset - start], chunk);
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val += chunk;
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offset += chunk;
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bytes -= chunk;
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}
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return 0;
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}
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static struct nvmem_config jz4780_efuse_nvmem_config = {
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.name = "jz4780-efuse",
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.size = 1024,
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.word_size = 1,
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.stride = 1,
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.owner = THIS_MODULE,
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.reg_read = jz4780_efuse_read,
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};
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static const struct regmap_config jz4780_efuse_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = JZ_EFUDATA(7),
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};
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static void clk_disable_unprepare_helper(void *clock)
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{
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clk_disable_unprepare(clock);
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}
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static int jz4780_efuse_probe(struct platform_device *pdev)
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{
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struct nvmem_device *nvmem;
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struct jz4780_efuse *efuse;
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struct nvmem_config cfg;
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unsigned long clk_rate;
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unsigned long rd_adj;
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unsigned long rd_strobe;
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struct device *dev = &pdev->dev;
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void __iomem *regs;
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int ret;
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efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
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if (!efuse)
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return -ENOMEM;
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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efuse->map = devm_regmap_init_mmio(dev, regs,
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&jz4780_efuse_regmap_config);
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if (IS_ERR(efuse->map))
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return PTR_ERR(efuse->map);
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efuse->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(efuse->clk))
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return PTR_ERR(efuse->clk);
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ret = clk_prepare_enable(efuse->clk);
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if (ret < 0)
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return ret;
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ret = devm_add_action_or_reset(&pdev->dev,
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clk_disable_unprepare_helper,
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efuse->clk);
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if (ret < 0)
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return ret;
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clk_rate = clk_get_rate(efuse->clk);
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efuse->dev = dev;
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/*
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* rd_adj and rd_strobe are 4 bit values
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* conditions:
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* bus clk_period * (rd_adj + 1) > 6.5ns
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* bus clk_period * (rd_adj + 5 + rd_strobe) > 35ns
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* i.e. rd_adj >= 6.5ns / clk_period
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* i.e. rd_strobe >= 35 ns / clk_period - 5 - rd_adj + 1
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* constants:
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* 1 / 6.5ns == 153846154 Hz
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* 1 / 35ns == 28571429 Hz
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*/
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rd_adj = clk_rate / 153846154;
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rd_strobe = clk_rate / 28571429 - 5 - rd_adj + 1;
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if (rd_adj > EFUCFG_RD_ADJ_MASK ||
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rd_strobe > EFUCFG_RD_STR_MASK) {
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dev_err(&pdev->dev, "Cannot set clock configuration\n");
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return -EINVAL;
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}
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regmap_update_bits(efuse->map, JZ_EFUCFG,
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(EFUCFG_RD_ADJ_MASK << EFUCFG_RD_ADJ_SHIFT) |
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(EFUCFG_RD_STR_MASK << EFUCFG_RD_STR_SHIFT),
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(rd_adj << EFUCFG_RD_ADJ_SHIFT) |
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(rd_strobe << EFUCFG_RD_STR_SHIFT));
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cfg = jz4780_efuse_nvmem_config;
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cfg.dev = &pdev->dev;
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cfg.priv = efuse;
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nvmem = devm_nvmem_register(dev, &cfg);
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if (IS_ERR(nvmem))
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return PTR_ERR(nvmem);
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return 0;
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}
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static const struct of_device_id jz4780_efuse_match[] = {
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{ .compatible = "ingenic,jz4780-efuse" },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, jz4780_efuse_match);
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static struct platform_driver jz4780_efuse_driver = {
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.probe = jz4780_efuse_probe,
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.driver = {
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.name = "jz4780-efuse",
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.of_match_table = jz4780_efuse_match,
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},
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};
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module_platform_driver(jz4780_efuse_driver);
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MODULE_AUTHOR("PrasannaKumar Muralidharan <prasannatsmkumar@gmail.com>");
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MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
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MODULE_AUTHOR("Paul Cercueil <paul@crapouillou.net>");
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MODULE_DESCRIPTION("Ingenic JZ4780 efuse driver");
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MODULE_LICENSE("GPL v2");
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