260 lines
6.0 KiB
C
260 lines
6.0 KiB
C
/*
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* drivers/pwm/pwm-tegra.c
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*
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* Tegra pulse-width-modulation controller driver
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*
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* Copyright (c) 2010, NVIDIA Corporation.
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* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/pwm.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#define PWM_ENABLE (1 << 31)
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#define PWM_DUTY_WIDTH 8
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#define PWM_DUTY_SHIFT 16
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#define PWM_SCALE_WIDTH 13
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#define PWM_SCALE_SHIFT 0
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#define NUM_PWM 4
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struct tegra_pwm_chip {
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struct pwm_chip chip;
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struct device *dev;
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struct clk *clk;
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void __iomem *mmio_base;
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};
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static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct tegra_pwm_chip, chip);
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}
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static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
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{
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return readl(chip->mmio_base + (num << 4));
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}
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static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
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unsigned long val)
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{
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writel(val, chip->mmio_base + (num << 4));
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}
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static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
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unsigned long long c;
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unsigned long rate, hz;
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u32 val = 0;
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int err;
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/*
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* Convert from duty_ns / period_ns to a fixed number of duty ticks
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* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
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* nearest integer during division.
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*/
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c = duty_ns * ((1 << PWM_DUTY_WIDTH) - 1) + period_ns / 2;
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do_div(c, period_ns);
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val = (u32)c << PWM_DUTY_SHIFT;
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/*
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* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
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* cycles at the PWM clock rate will take period_ns nanoseconds.
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*/
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rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH;
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hz = 1000000000ul / period_ns;
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rate = (rate + (hz / 2)) / hz;
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/*
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* Since the actual PWM divider is the register's frequency divider
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* field minus 1, we need to decrement to get the correct value to
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* write to the register.
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*/
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if (rate > 0)
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rate--;
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/*
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* Make sure that the rate will fit in the register's frequency
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* divider field.
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*/
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if (rate >> PWM_SCALE_WIDTH)
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return -EINVAL;
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val |= rate << PWM_SCALE_SHIFT;
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/*
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* If the PWM channel is disabled, make sure to turn on the clock
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* before writing the register. Otherwise, keep it enabled.
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*/
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if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
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err = clk_prepare_enable(pc->clk);
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if (err < 0)
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return err;
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} else
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val |= PWM_ENABLE;
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pwm_writel(pc, pwm->hwpwm, val);
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/*
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* If the PWM is not enabled, turn the clock off again to save power.
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*/
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if (!test_bit(PWMF_ENABLED, &pwm->flags))
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clk_disable_unprepare(pc->clk);
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return 0;
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}
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static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
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int rc = 0;
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u32 val;
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rc = clk_prepare_enable(pc->clk);
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if (rc < 0)
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return rc;
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val = pwm_readl(pc, pwm->hwpwm);
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val |= PWM_ENABLE;
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pwm_writel(pc, pwm->hwpwm, val);
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return 0;
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}
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static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
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u32 val;
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val = pwm_readl(pc, pwm->hwpwm);
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val &= ~PWM_ENABLE;
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pwm_writel(pc, pwm->hwpwm, val);
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clk_disable_unprepare(pc->clk);
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}
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static const struct pwm_ops tegra_pwm_ops = {
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.config = tegra_pwm_config,
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.enable = tegra_pwm_enable,
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.disable = tegra_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int tegra_pwm_probe(struct platform_device *pdev)
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{
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struct tegra_pwm_chip *pwm;
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struct resource *r;
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int ret;
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pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
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if (!pwm) {
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dev_err(&pdev->dev, "failed to allocate memory\n");
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return -ENOMEM;
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}
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pwm->dev = &pdev->dev;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no memory resources defined\n");
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return -ENODEV;
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}
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pwm->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
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if (!pwm->mmio_base)
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return -EADDRNOTAVAIL;
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platform_set_drvdata(pdev, pwm);
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pwm->clk = devm_clk_get(&pdev->dev, NULL);
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if (IS_ERR(pwm->clk))
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return PTR_ERR(pwm->clk);
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pwm->chip.dev = &pdev->dev;
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pwm->chip.ops = &tegra_pwm_ops;
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pwm->chip.base = -1;
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pwm->chip.npwm = NUM_PWM;
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ret = pwmchip_add(&pwm->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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return 0;
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}
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static int __devexit tegra_pwm_remove(struct platform_device *pdev)
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{
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struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
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int i;
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if (WARN_ON(!pc))
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return -ENODEV;
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for (i = 0; i < NUM_PWM; i++) {
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struct pwm_device *pwm = &pc->chip.pwms[i];
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if (!test_bit(PWMF_ENABLED, &pwm->flags))
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if (clk_prepare_enable(pc->clk) < 0)
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continue;
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pwm_writel(pc, i, 0);
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clk_disable_unprepare(pc->clk);
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}
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return pwmchip_remove(&pc->chip);
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}
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#ifdef CONFIG_OF
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static struct of_device_id tegra_pwm_of_match[] = {
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{ .compatible = "nvidia,tegra20-pwm" },
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{ .compatible = "nvidia,tegra30-pwm" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
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#endif
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static struct platform_driver tegra_pwm_driver = {
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.driver = {
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.name = "tegra-pwm",
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.of_match_table = of_match_ptr(tegra_pwm_of_match),
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},
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.probe = tegra_pwm_probe,
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.remove = __devexit_p(tegra_pwm_remove),
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};
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module_platform_driver(tegra_pwm_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("NVIDIA Corporation");
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MODULE_ALIAS("platform:tegra-pwm");
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