366 lines
9.5 KiB
C
366 lines
9.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Microchip Technology
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mii.h>
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#include <linux/ethtool.h>
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#include <linux/phy.h>
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#include <linux/microchipphy.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <dt-bindings/net/microchip-lan78xx.h>
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#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
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#define DRIVER_DESC "Microchip LAN88XX PHY driver"
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struct lan88xx_priv {
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int chip_id;
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int chip_rev;
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__u32 wolopts;
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};
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static int lan88xx_read_page(struct phy_device *phydev)
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{
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return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
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}
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static int lan88xx_write_page(struct phy_device *phydev, int page)
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{
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return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
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}
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static int lan88xx_phy_config_intr(struct phy_device *phydev)
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{
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int rc;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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/* unmask all source and clear them before enable */
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rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
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rc = phy_read(phydev, LAN88XX_INT_STS);
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rc = phy_write(phydev, LAN88XX_INT_MASK,
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LAN88XX_INT_MASK_MDINTPIN_EN_ |
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LAN88XX_INT_MASK_LINK_CHANGE_);
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} else {
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rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
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}
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return rc < 0 ? rc : 0;
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}
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static int lan88xx_phy_ack_interrupt(struct phy_device *phydev)
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{
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int rc = phy_read(phydev, LAN88XX_INT_STS);
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return rc < 0 ? rc : 0;
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}
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static int lan88xx_suspend(struct phy_device *phydev)
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{
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struct lan88xx_priv *priv = phydev->priv;
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/* do not power down PHY when WOL is enabled */
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if (!priv->wolopts)
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genphy_suspend(phydev);
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return 0;
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}
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static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
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u32 data)
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{
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int val, save_page, ret = 0;
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u16 buf;
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/* Save current page */
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save_page = phy_save_page(phydev);
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if (save_page < 0) {
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phydev_warn(phydev, "Failed to get current page\n");
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goto err;
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}
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/* Switch to TR page */
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lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
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ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
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(data & 0xFFFF));
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if (ret < 0) {
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phydev_warn(phydev, "Failed to write TR low data\n");
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goto err;
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}
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ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
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(data & 0x00FF0000) >> 16);
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if (ret < 0) {
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phydev_warn(phydev, "Failed to write TR high data\n");
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goto err;
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}
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/* Config control bits [15:13] of register */
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buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
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buf |= 0x8000; /* Set [15] to Packet transmit */
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ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
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if (ret < 0) {
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phydev_warn(phydev, "Failed to write data in reg\n");
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goto err;
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}
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usleep_range(1000, 2000);/* Wait for Data to be written */
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val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
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if (!(val & 0x8000))
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phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
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regaddr);
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err:
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return phy_restore_page(phydev, save_page, ret);
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}
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static void lan88xx_config_TR_regs(struct phy_device *phydev)
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{
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int err;
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/* Get access to Channel 0x1, Node 0xF , Register 0x01.
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* Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
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* MrvlTrFix1000Kp, MasterEnableTR bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x06.
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* Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
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* SSTrKp1000Mas bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
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/* Get access to Channel b'10, Node b'1111, Register 0x11.
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* Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
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* bits
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*/
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err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x10.
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* Write 24-bit value 0xEEFFDD to register. Setting
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* eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
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* eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x13.
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* Write 24-bit value 0x071448 to register. Setting
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* slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x12.
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* Write 24-bit value 0x13132F to register. Setting
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* slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x14.
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* Write 24-bit value 0x0 to register. Setting eee_3level_delay,
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* eee_TrKf_freeze_delay bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
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/* Get access to Channel b'01, Node b'1111, Register 0x34.
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* Write 24-bit value 0x91B06C to register. Setting
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* FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
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* FastMseSearchUpdGain1000 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
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/* Get access to Channel b'01, Node b'1111, Register 0x3E.
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* Write 24-bit value 0xC0A028 to register. Setting
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* FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
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* FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
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/* Get access to Channel b'01, Node b'1111, Register 0x35.
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* Write 24-bit value 0x041600 to register. Setting
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* FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
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* FastMsePhChangeDelay1000 bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
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/* Get access to Channel b'10, Node b'1101, Register 0x03.
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* Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
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*/
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err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
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if (err < 0)
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phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
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}
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static int lan88xx_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct lan88xx_priv *priv;
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u32 led_modes[4];
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int len;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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priv->wolopts = 0;
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len = of_property_read_variable_u32_array(dev->of_node,
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"microchip,led-modes",
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led_modes,
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0,
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ARRAY_SIZE(led_modes));
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if (len >= 0) {
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u32 reg = 0;
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int i;
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for (i = 0; i < len; i++) {
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if (led_modes[i] > 15)
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return -EINVAL;
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reg |= led_modes[i] << (i * 4);
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}
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for (; i < ARRAY_SIZE(led_modes); i++)
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reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
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(void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
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} else if (len == -EOVERFLOW) {
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return -EINVAL;
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}
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/* these values can be used to identify internal PHY */
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priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
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priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
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phydev->priv = priv;
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return 0;
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}
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static void lan88xx_remove(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct lan88xx_priv *priv = phydev->priv;
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if (priv)
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devm_kfree(dev, priv);
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}
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static int lan88xx_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct lan88xx_priv *priv = phydev->priv;
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priv->wolopts = wol->wolopts;
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return 0;
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}
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static void lan88xx_set_mdix(struct phy_device *phydev)
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{
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int buf;
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int val;
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switch (phydev->mdix_ctrl) {
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case ETH_TP_MDI:
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val = LAN88XX_EXT_MODE_CTRL_MDI_;
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break;
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case ETH_TP_MDI_X:
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val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
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break;
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case ETH_TP_MDI_AUTO:
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val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
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break;
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default:
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return;
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}
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
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buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
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buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
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buf |= val;
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phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
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phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
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}
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static int lan88xx_config_init(struct phy_device *phydev)
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{
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int val;
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genphy_config_init(phydev);
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/*Zerodetect delay enable */
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val = phy_read_mmd(phydev, MDIO_MMD_PCS,
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PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
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val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
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phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
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val);
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/* Config DSP registers */
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lan88xx_config_TR_regs(phydev);
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return 0;
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}
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static int lan88xx_config_aneg(struct phy_device *phydev)
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{
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lan88xx_set_mdix(phydev);
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return genphy_config_aneg(phydev);
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}
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static struct phy_driver microchip_phy_driver[] = {
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{
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.phy_id = 0x0007c130,
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.phy_id_mask = 0xfffffff0,
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.name = "Microchip LAN88xx",
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/* PHY_GBIT_FEATURES */
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.probe = lan88xx_probe,
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.remove = lan88xx_remove,
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.config_init = lan88xx_config_init,
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.config_aneg = lan88xx_config_aneg,
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.ack_interrupt = lan88xx_phy_ack_interrupt,
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.config_intr = lan88xx_phy_config_intr,
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.suspend = lan88xx_suspend,
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.resume = genphy_resume,
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.set_wol = lan88xx_set_wol,
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.read_page = lan88xx_read_page,
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.write_page = lan88xx_write_page,
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} };
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module_phy_driver(microchip_phy_driver);
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static struct mdio_device_id __maybe_unused microchip_tbl[] = {
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{ 0x0007c130, 0xfffffff0 },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, microchip_tbl);
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MODULE_AUTHOR(DRIVER_AUTHOR);
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MODULE_DESCRIPTION(DRIVER_DESC);
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MODULE_LICENSE("GPL");
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