437 lines
11 KiB
C
437 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* drivers/net/phy/at803x.c
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*
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* Driver for Atheros 803x PHY
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*
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* Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
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*/
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#include <linux/phy.h>
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#include <linux/module.h>
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#include <linux/string.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/of_gpio.h>
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#include <linux/gpio/consumer.h>
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#define AT803X_INTR_ENABLE 0x12
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#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
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#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
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#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
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#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
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#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
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#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
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#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
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#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
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#define AT803X_INTR_ENABLE_WOL BIT(0)
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#define AT803X_INTR_STATUS 0x13
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#define AT803X_SMART_SPEED 0x14
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#define AT803X_LED_CONTROL 0x18
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#define AT803X_DEVICE_ADDR 0x03
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#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
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#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
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#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
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#define AT803X_REG_CHIP_CONFIG 0x1f
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#define AT803X_BT_BX_REG_SEL 0x8000
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#define AT803X_DEBUG_ADDR 0x1D
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#define AT803X_DEBUG_DATA 0x1E
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#define AT803X_MODE_CFG_MASK 0x0F
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#define AT803X_MODE_CFG_SGMII 0x01
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#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
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#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
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#define AT803X_DEBUG_REG_0 0x00
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#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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#define ATH8035_PHY_ID 0x004dd072
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#define AT803X_PHY_ID_MASK 0xffffffef
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MODULE_DESCRIPTION("Atheros 803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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struct at803x_priv {
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bool phy_reset:1;
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};
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struct at803x_context {
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u16 bmcr;
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u16 advertise;
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u16 control1000;
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u16 int_enable;
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u16 smart_speed;
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u16 led_control;
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};
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static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
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{
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int ret;
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ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
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if (ret < 0)
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return ret;
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return phy_read(phydev, AT803X_DEBUG_DATA);
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}
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static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
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u16 clear, u16 set)
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{
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u16 val;
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int ret;
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ret = at803x_debug_reg_read(phydev, reg);
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if (ret < 0)
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return ret;
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val = ret & 0xffff;
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val &= ~clear;
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val |= set;
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return phy_write(phydev, AT803X_DEBUG_DATA, val);
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}
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static int at803x_enable_rx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0, 0,
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AT803X_DEBUG_RX_CLK_DLY_EN);
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}
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static int at803x_enable_tx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5, 0,
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AT803X_DEBUG_TX_CLK_DLY_EN);
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}
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static int at803x_disable_rx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_0,
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AT803X_DEBUG_RX_CLK_DLY_EN, 0);
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}
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static int at803x_disable_tx_delay(struct phy_device *phydev)
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{
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_5,
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AT803X_DEBUG_TX_CLK_DLY_EN, 0);
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}
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/* save relevant PHY registers to private copy */
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static void at803x_context_save(struct phy_device *phydev,
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struct at803x_context *context)
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{
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context->bmcr = phy_read(phydev, MII_BMCR);
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context->advertise = phy_read(phydev, MII_ADVERTISE);
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context->control1000 = phy_read(phydev, MII_CTRL1000);
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context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
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context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
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context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
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}
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/* restore relevant PHY registers from private copy */
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static void at803x_context_restore(struct phy_device *phydev,
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const struct at803x_context *context)
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{
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phy_write(phydev, MII_BMCR, context->bmcr);
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phy_write(phydev, MII_ADVERTISE, context->advertise);
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phy_write(phydev, MII_CTRL1000, context->control1000);
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phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
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phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
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phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
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}
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static int at803x_set_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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struct net_device *ndev = phydev->attached_dev;
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const u8 *mac;
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int ret;
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u32 value;
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unsigned int i, offsets[] = {
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AT803X_LOC_MAC_ADDR_32_47_OFFSET,
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AT803X_LOC_MAC_ADDR_16_31_OFFSET,
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AT803X_LOC_MAC_ADDR_0_15_OFFSET,
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};
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if (!ndev)
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return -ENODEV;
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if (wol->wolopts & WAKE_MAGIC) {
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mac = (const u8 *) ndev->dev_addr;
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if (!is_valid_ether_addr(mac))
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return -EINVAL;
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for (i = 0; i < 3; i++)
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phy_write_mmd(phydev, AT803X_DEVICE_ADDR, offsets[i],
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mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
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value = phy_read(phydev, AT803X_INTR_ENABLE);
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value |= AT803X_INTR_ENABLE_WOL;
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ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
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if (ret)
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return ret;
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value = phy_read(phydev, AT803X_INTR_STATUS);
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} else {
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value = phy_read(phydev, AT803X_INTR_ENABLE);
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value &= (~AT803X_INTR_ENABLE_WOL);
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ret = phy_write(phydev, AT803X_INTR_ENABLE, value);
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if (ret)
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return ret;
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value = phy_read(phydev, AT803X_INTR_STATUS);
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}
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return ret;
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}
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static void at803x_get_wol(struct phy_device *phydev,
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struct ethtool_wolinfo *wol)
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{
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u32 value;
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wol->supported = WAKE_MAGIC;
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wol->wolopts = 0;
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value = phy_read(phydev, AT803X_INTR_ENABLE);
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if (value & AT803X_INTR_ENABLE_WOL)
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wol->wolopts |= WAKE_MAGIC;
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}
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static int at803x_suspend(struct phy_device *phydev)
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{
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int value;
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int wol_enabled;
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value = phy_read(phydev, AT803X_INTR_ENABLE);
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wol_enabled = value & AT803X_INTR_ENABLE_WOL;
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if (wol_enabled)
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value = BMCR_ISOLATE;
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else
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value = BMCR_PDOWN;
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phy_modify(phydev, MII_BMCR, 0, value);
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return 0;
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}
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static int at803x_resume(struct phy_device *phydev)
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{
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return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
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}
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static int at803x_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct at803x_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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return 0;
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}
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static int at803x_config_init(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_config_init(phydev);
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if (ret < 0)
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return ret;
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/* The RX and TX delay default is:
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* after HW reset: RX delay enabled and TX delay disabled
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* after SW reset: RX delay enabled, while TX delay retains the
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* value before reset.
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*
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* So let's first disable the RX and TX delays in PHY and enable
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* them based on the mode selected (this also takes care of RGMII
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* mode where we expect delays to be disabled)
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*/
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ret = at803x_disable_rx_delay(phydev);
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if (ret < 0)
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return ret;
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ret = at803x_disable_tx_delay(phydev);
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if (ret < 0)
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return ret;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
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/* If RGMII_ID or RGMII_RXID are specified enable RX delay,
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* otherwise keep it disabled
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*/
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ret = at803x_enable_rx_delay(phydev);
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if (ret < 0)
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return ret;
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}
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
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/* If RGMII_ID or RGMII_TXID are specified enable TX delay,
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* otherwise keep it disabled
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*/
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ret = at803x_enable_tx_delay(phydev);
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}
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return ret;
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}
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static int at803x_ack_interrupt(struct phy_device *phydev)
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{
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int err;
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err = phy_read(phydev, AT803X_INTR_STATUS);
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return (err < 0) ? err : 0;
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}
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static int at803x_config_intr(struct phy_device *phydev)
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{
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int err;
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int value;
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value = phy_read(phydev, AT803X_INTR_ENABLE);
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
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value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
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value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
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value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
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value |= AT803X_INTR_ENABLE_LINK_FAIL;
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value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
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err = phy_write(phydev, AT803X_INTR_ENABLE, value);
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}
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else
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err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
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return err;
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}
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static void at803x_link_change_notify(struct phy_device *phydev)
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{
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/*
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* Conduct a hardware reset for AT8030 every time a link loss is
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* signalled. This is necessary to circumvent a hardware bug that
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* occurs when the cable is unplugged while TX packets are pending
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* in the FIFO. In such cases, the FIFO enters an error mode it
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* cannot recover from by software.
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*/
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if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
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struct at803x_context context;
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at803x_context_save(phydev, &context);
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phy_device_reset(phydev, 1);
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msleep(1);
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phy_device_reset(phydev, 0);
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msleep(1);
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at803x_context_restore(phydev, &context);
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phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
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}
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}
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static int at803x_aneg_done(struct phy_device *phydev)
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{
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int ccr;
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int aneg_done = genphy_aneg_done(phydev);
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if (aneg_done != BMSR_ANEGCOMPLETE)
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return aneg_done;
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/*
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* in SGMII mode, if copper side autoneg is successful,
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* also check SGMII side autoneg result
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*/
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ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
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if ((ccr & AT803X_MODE_CFG_MASK) != AT803X_MODE_CFG_SGMII)
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return aneg_done;
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/* switch to SGMII/fiber page */
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phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr & ~AT803X_BT_BX_REG_SEL);
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/* check if the SGMII link is OK. */
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if (!(phy_read(phydev, AT803X_PSSR) & AT803X_PSSR_MR_AN_COMPLETE)) {
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phydev_warn(phydev, "803x_aneg_done: SGMII link is not ok\n");
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aneg_done = 0;
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}
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/* switch back to copper page */
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phy_write(phydev, AT803X_REG_CHIP_CONFIG, ccr | AT803X_BT_BX_REG_SEL);
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return aneg_done;
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}
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static struct phy_driver at803x_driver[] = {
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{
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/* ATHEROS 8035 */
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.phy_id = ATH8035_PHY_ID,
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.name = "Atheros 8035 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.set_wol = at803x_set_wol,
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.get_wol = at803x_get_wol,
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.suspend = at803x_suspend,
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.resume = at803x_resume,
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/* PHY_GBIT_FEATURES */
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.ack_interrupt = at803x_ack_interrupt,
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.config_intr = at803x_config_intr,
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}, {
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/* ATHEROS 8030 */
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.phy_id = ATH8030_PHY_ID,
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.name = "Atheros 8030 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.link_change_notify = at803x_link_change_notify,
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.set_wol = at803x_set_wol,
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.get_wol = at803x_get_wol,
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.suspend = at803x_suspend,
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.resume = at803x_resume,
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/* PHY_BASIC_FEATURES */
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.ack_interrupt = at803x_ack_interrupt,
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.config_intr = at803x_config_intr,
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}, {
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/* ATHEROS 8031 */
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.phy_id = ATH8031_PHY_ID,
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.name = "Atheros 8031 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.set_wol = at803x_set_wol,
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.get_wol = at803x_get_wol,
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.suspend = at803x_suspend,
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.resume = at803x_resume,
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/* PHY_GBIT_FEATURES */
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.aneg_done = at803x_aneg_done,
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.ack_interrupt = &at803x_ack_interrupt,
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.config_intr = &at803x_config_intr,
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} };
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module_phy_driver(at803x_driver);
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static struct mdio_device_id __maybe_unused atheros_tbl[] = {
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{ ATH8030_PHY_ID, AT803X_PHY_ID_MASK },
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{ ATH8031_PHY_ID, AT803X_PHY_ID_MASK },
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{ ATH8035_PHY_ID, AT803X_PHY_ID_MASK },
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{ }
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};
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MODULE_DEVICE_TABLE(mdio, atheros_tbl);
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