695 lines
19 KiB
C
695 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Aquantia PHY
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*
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* Author: Shaohui Xie <Shaohui.Xie@freescale.com>
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*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/bitfield.h>
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#include <linux/phy.h>
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#include "aquantia.h"
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#define PHY_ID_AQ1202 0x03a1b445
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#define PHY_ID_AQ2104 0x03a1b460
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#define PHY_ID_AQR105 0x03a1b4a2
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#define PHY_ID_AQR106 0x03a1b4d0
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#define PHY_ID_AQR107 0x03a1b4e0
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#define PHY_ID_AQCS109 0x03a1b5c2
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#define PHY_ID_AQR405 0x03a1b4b0
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#define MDIO_PHYXS_VEND_IF_STATUS 0xe812
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3)
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
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#define MDIO_AN_VEND_PROV 0xc400
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#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
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#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
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#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
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#define MDIO_AN_TX_VEND_STATUS1 0xc800
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#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
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#define MDIO_AN_TX_VEND_STATUS1_10BASET 0
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#define MDIO_AN_TX_VEND_STATUS1_100BASETX 1
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#define MDIO_AN_TX_VEND_STATUS1_1000BASET 2
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#define MDIO_AN_TX_VEND_STATUS1_10GBASET 3
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#define MDIO_AN_TX_VEND_STATUS1_2500BASET 4
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#define MDIO_AN_TX_VEND_STATUS1_5000BASET 5
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#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0)
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#define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00
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#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1)
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#define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01
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#define MDIO_AN_TX_VEND_INT_MASK2 0xd401
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#define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0)
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#define MDIO_AN_RX_LP_STAT1 0xe820
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#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15)
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#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14)
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#define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13)
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#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12)
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#define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2)
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#define MDIO_AN_RX_LP_STAT4 0xe823
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#define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8)
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#define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0)
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#define MDIO_AN_RX_VEND_STAT3 0xe832
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#define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
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/* MDIO_MMD_C22EXT */
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#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
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#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
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#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
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#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
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#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
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#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
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#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
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#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
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#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
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#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
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/* Vendor specific 1, MDIO_MMD_VEND1 */
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#define VEND1_GLOBAL_FW_ID 0x0020
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#define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
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#define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0)
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#define VEND1_GLOBAL_RSVD_STAT1 0xc885
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#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4)
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#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0)
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#define VEND1_GLOBAL_RSVD_STAT9 0xc88d
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#define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0)
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#define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23
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#define VEND1_GLOBAL_INT_STD_STATUS 0xfc00
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#define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01
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#define VEND1_GLOBAL_INT_STD_MASK 0xff00
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#define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15)
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#define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12)
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#define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10)
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#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9)
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#define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8)
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#define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7)
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#define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6)
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#define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0)
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#define VEND1_GLOBAL_INT_VEND_MASK 0xff01
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#define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15)
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#define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14)
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#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13)
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#define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12)
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#define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
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#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
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struct aqr107_hw_stat {
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const char *name;
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int reg;
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int size;
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};
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#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
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static const struct aqr107_hw_stat aqr107_hw_stats[] = {
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SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
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SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
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SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
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SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
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SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
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SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
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SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
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SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
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SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
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SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
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};
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#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
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struct aqr107_priv {
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u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
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};
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static int aqr107_get_sset_count(struct phy_device *phydev)
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{
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return AQR107_SGMII_STAT_SZ;
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}
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static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
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{
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int i;
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for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
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strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
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ETH_GSTRING_LEN);
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}
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static u64 aqr107_get_stat(struct phy_device *phydev, int index)
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{
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const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
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int len_l = min(stat->size, 16);
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int len_h = stat->size - len_l;
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u64 ret;
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
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if (val < 0)
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return U64_MAX;
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ret = val & GENMASK(len_l - 1, 0);
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if (len_h) {
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val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
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if (val < 0)
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return U64_MAX;
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ret += (val & GENMASK(len_h - 1, 0)) << 16;
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}
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return ret;
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}
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static void aqr107_get_stats(struct phy_device *phydev,
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struct ethtool_stats *stats, u64 *data)
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{
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struct aqr107_priv *priv = phydev->priv;
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u64 val;
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int i;
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for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
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val = aqr107_get_stat(phydev, i);
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if (val == U64_MAX)
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phydev_err(phydev, "Reading HW Statistics failed for %s\n",
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aqr107_hw_stats[i].name);
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else
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priv->sgmii_stats[i] += val;
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data[i] = priv->sgmii_stats[i];
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}
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}
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static int aqr_config_aneg(struct phy_device *phydev)
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{
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bool changed = false;
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u16 reg;
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int ret;
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if (phydev->autoneg == AUTONEG_DISABLE)
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return genphy_c45_pma_setup_forced(phydev);
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ret = genphy_c45_an_config_aneg(phydev);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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/* Clause 45 has no standardized support for 1000BaseT, therefore
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* use vendor registers for this mode.
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*/
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reg = 0;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->advertising))
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reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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phydev->advertising))
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reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
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MDIO_AN_VEND_PROV_1000BASET_HALF |
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MDIO_AN_VEND_PROV_1000BASET_FULL, reg);
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if (ret < 0)
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return ret;
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if (ret > 0)
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changed = true;
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return genphy_c45_check_and_restart_aneg(phydev, changed);
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}
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static int aqr_config_intr(struct phy_device *phydev)
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{
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bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
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int err;
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err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
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en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
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if (err < 0)
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return err;
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err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
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en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
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if (err < 0)
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return err;
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return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
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en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
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VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
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}
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static int aqr_ack_interrupt(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read_mmd(phydev, MDIO_MMD_AN,
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MDIO_AN_TX_VEND_INT_STATUS2);
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return (reg < 0) ? reg : 0;
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}
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static int aqr_read_status(struct phy_device *phydev)
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{
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int val;
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if (phydev->autoneg == AUTONEG_ENABLE) {
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
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if (val < 0)
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return val;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
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phydev->lp_advertising,
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val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
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linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
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phydev->lp_advertising,
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val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
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}
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return genphy_c45_read_status(phydev);
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}
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static int aqr107_read_downshift_event(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1);
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if (val < 0)
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return val;
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return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT);
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}
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static int aqr107_read_rate(struct phy_device *phydev)
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{
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int val;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
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if (val < 0)
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return val;
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switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
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case MDIO_AN_TX_VEND_STATUS1_10BASET:
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phydev->speed = SPEED_10;
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break;
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case MDIO_AN_TX_VEND_STATUS1_100BASETX:
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phydev->speed = SPEED_100;
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break;
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case MDIO_AN_TX_VEND_STATUS1_1000BASET:
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phydev->speed = SPEED_1000;
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break;
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case MDIO_AN_TX_VEND_STATUS1_2500BASET:
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phydev->speed = SPEED_2500;
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break;
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case MDIO_AN_TX_VEND_STATUS1_5000BASET:
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phydev->speed = SPEED_5000;
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break;
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case MDIO_AN_TX_VEND_STATUS1_10GBASET:
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phydev->speed = SPEED_10000;
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break;
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default:
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phydev->speed = SPEED_UNKNOWN;
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break;
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}
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if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
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phydev->duplex = DUPLEX_FULL;
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else
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phydev->duplex = DUPLEX_HALF;
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return 0;
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}
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static int aqr107_read_status(struct phy_device *phydev)
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{
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int val, ret;
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ret = aqr_read_status(phydev);
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if (ret)
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return ret;
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if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
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return 0;
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val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
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if (val < 0)
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return val;
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switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
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phydev->interface = PHY_INTERFACE_MODE_10GKR;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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break;
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case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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break;
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default:
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phydev->interface = PHY_INTERFACE_MODE_NA;
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break;
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}
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val = aqr107_read_downshift_event(phydev);
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if (val <= 0)
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return val;
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phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n");
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/* Read downshifted rate from vendor register */
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return aqr107_read_rate(phydev);
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}
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static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
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{
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int val, cnt, enable;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
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if (val < 0)
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return val;
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enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
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cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
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*data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
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return 0;
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}
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static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
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{
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int val = 0;
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if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
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return -E2BIG;
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if (cnt != DOWNSHIFT_DEV_DISABLE) {
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val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
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val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
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}
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return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
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MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
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MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
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}
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static int aqr107_get_tunable(struct phy_device *phydev,
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struct ethtool_tunable *tuna, void *data)
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{
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switch (tuna->id) {
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case ETHTOOL_PHY_DOWNSHIFT:
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return aqr107_get_downshift(phydev, data);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
static int aqr107_set_tunable(struct phy_device *phydev,
|
|
struct ethtool_tunable *tuna, const void *data)
|
|
{
|
|
switch (tuna->id) {
|
|
case ETHTOOL_PHY_DOWNSHIFT:
|
|
return aqr107_set_downshift(phydev, *(const u8 *)data);
|
|
default:
|
|
return -EOPNOTSUPP;
|
|
}
|
|
}
|
|
|
|
/* If we configure settings whilst firmware is still initializing the chip,
|
|
* then these settings may be overwritten. Therefore make sure chip
|
|
* initialization has completed. Use presence of the firmware ID as
|
|
* indicator for initialization having completed.
|
|
* The chip also provides a "reset completed" bit, but it's cleared after
|
|
* read. Therefore function would time out if called again.
|
|
*/
|
|
static int aqr107_wait_reset_complete(struct phy_device *phydev)
|
|
{
|
|
int val, retries = 100;
|
|
|
|
do {
|
|
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
|
|
if (val < 0)
|
|
return val;
|
|
msleep(20);
|
|
} while (!val && --retries);
|
|
|
|
return val ? 0 : -ETIMEDOUT;
|
|
}
|
|
|
|
static void aqr107_chip_info(struct phy_device *phydev)
|
|
{
|
|
u8 fw_major, fw_minor, build_id, prov_id;
|
|
int val;
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
|
|
if (val < 0)
|
|
return;
|
|
|
|
fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
|
|
fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
|
|
if (val < 0)
|
|
return;
|
|
|
|
build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
|
|
prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
|
|
|
|
phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
|
|
fw_major, fw_minor, build_id, prov_id);
|
|
}
|
|
|
|
static int aqr107_config_init(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
/* Check that the PHY interface type is compatible */
|
|
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
|
|
phydev->interface != PHY_INTERFACE_MODE_XGMII &&
|
|
phydev->interface != PHY_INTERFACE_MODE_10GKR)
|
|
return -ENODEV;
|
|
|
|
ret = aqr107_wait_reset_complete(phydev);
|
|
if (!ret)
|
|
aqr107_chip_info(phydev);
|
|
|
|
/* ensure that a latched downshift event is cleared */
|
|
aqr107_read_downshift_event(phydev);
|
|
|
|
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
|
|
}
|
|
|
|
static int aqcs109_config_init(struct phy_device *phydev)
|
|
{
|
|
int ret;
|
|
|
|
/* Check that the PHY interface type is compatible */
|
|
if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
|
|
phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
|
|
return -ENODEV;
|
|
|
|
ret = aqr107_wait_reset_complete(phydev);
|
|
if (!ret)
|
|
aqr107_chip_info(phydev);
|
|
|
|
/* AQCS109 belongs to a chip family partially supporting 10G and 5G.
|
|
* PMA speed ability bits are the same for all members of the family,
|
|
* AQCS109 however supports speeds up to 2.5G only.
|
|
*/
|
|
ret = phy_set_max_speed(phydev, SPEED_2500);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* ensure that a latched downshift event is cleared */
|
|
aqr107_read_downshift_event(phydev);
|
|
|
|
return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
|
|
}
|
|
|
|
static void aqr107_link_change_notify(struct phy_device *phydev)
|
|
{
|
|
u8 fw_major, fw_minor;
|
|
bool downshift, short_reach, afr;
|
|
int mode, val;
|
|
|
|
if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
|
|
return;
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
|
|
/* call failed or link partner is no Aquantia PHY */
|
|
if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
|
|
return;
|
|
|
|
short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
|
|
downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
|
|
if (val < 0)
|
|
return;
|
|
|
|
fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
|
|
fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
|
|
if (val < 0)
|
|
return;
|
|
|
|
afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
|
|
|
|
phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
|
|
fw_major, fw_minor,
|
|
short_reach ? ", short reach mode" : "",
|
|
downshift ? ", fast-retrain downshift advertised" : "",
|
|
afr ? ", fast reframe advertised" : "");
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
|
|
if (val < 0)
|
|
return;
|
|
|
|
mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
|
|
if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
|
|
phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
|
|
}
|
|
|
|
static int aqr107_suspend(struct phy_device *phydev)
|
|
{
|
|
return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
|
|
MDIO_CTRL1_LPOWER);
|
|
}
|
|
|
|
static int aqr107_resume(struct phy_device *phydev)
|
|
{
|
|
return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
|
|
MDIO_CTRL1_LPOWER);
|
|
}
|
|
|
|
static int aqr107_probe(struct phy_device *phydev)
|
|
{
|
|
phydev->priv = devm_kzalloc(&phydev->mdio.dev,
|
|
sizeof(struct aqr107_priv), GFP_KERNEL);
|
|
if (!phydev->priv)
|
|
return -ENOMEM;
|
|
|
|
return aqr_hwmon_probe(phydev);
|
|
}
|
|
|
|
static struct phy_driver aqr_driver[] = {
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
|
|
.name = "Aquantia AQ1202",
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
|
|
.name = "Aquantia AQ2104",
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
|
|
.name = "Aquantia AQR105",
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
|
|
.name = "Aquantia AQR106",
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
|
|
.name = "Aquantia AQR107",
|
|
.probe = aqr107_probe,
|
|
.config_init = aqr107_config_init,
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr107_read_status,
|
|
.get_tunable = aqr107_get_tunable,
|
|
.set_tunable = aqr107_set_tunable,
|
|
.suspend = aqr107_suspend,
|
|
.resume = aqr107_resume,
|
|
.get_sset_count = aqr107_get_sset_count,
|
|
.get_strings = aqr107_get_strings,
|
|
.get_stats = aqr107_get_stats,
|
|
.link_change_notify = aqr107_link_change_notify,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
|
|
.name = "Aquantia AQCS109",
|
|
.probe = aqr107_probe,
|
|
.config_init = aqcs109_config_init,
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr107_read_status,
|
|
.get_tunable = aqr107_get_tunable,
|
|
.set_tunable = aqr107_set_tunable,
|
|
.suspend = aqr107_suspend,
|
|
.resume = aqr107_resume,
|
|
.get_sset_count = aqr107_get_sset_count,
|
|
.get_strings = aqr107_get_strings,
|
|
.get_stats = aqr107_get_stats,
|
|
.link_change_notify = aqr107_link_change_notify,
|
|
},
|
|
{
|
|
PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
|
|
.name = "Aquantia AQR405",
|
|
.config_aneg = aqr_config_aneg,
|
|
.config_intr = aqr_config_intr,
|
|
.ack_interrupt = aqr_ack_interrupt,
|
|
.read_status = aqr_read_status,
|
|
},
|
|
};
|
|
|
|
module_phy_driver(aqr_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused aqr_tbl[] = {
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
|
|
{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, aqr_tbl);
|
|
|
|
MODULE_DESCRIPTION("Aquantia PHY driver");
|
|
MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
|
|
MODULE_LICENSE("GPL v2");
|