171 lines
3.9 KiB
C
171 lines
3.9 KiB
C
/*
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* arch/arm/plat-iop/time.c
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*
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* Timer code for IOP32x and IOP33x based systems
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*
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* Author: Deepak Saxena <dsaxena@mvista.com>
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*
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* Copyright 2002-2003 MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/io.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/export.h>
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#include <linux/sched_clock.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/uaccess.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/time.h>
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#include <mach/time.h>
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/*
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* Minimum clocksource/clockevent timer range in seconds
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*/
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#define IOP_MIN_RANGE 4
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/*
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* IOP clocksource (free-running timer 1).
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*/
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static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
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{
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return 0xffffffffu - read_tcr1();
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}
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static struct clocksource iop_clocksource = {
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.name = "iop_timer1",
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.rating = 300,
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.read = iop_clocksource_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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/*
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* IOP sched_clock() implementation via its clocksource.
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*/
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static u32 notrace iop_read_sched_clock(void)
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{
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return 0xffffffffu - read_tcr1();
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}
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/*
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* IOP clockevents (interrupting timer 0).
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*/
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static int iop_set_next_event(unsigned long delta,
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struct clock_event_device *unused)
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{
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u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
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BUG_ON(delta == 0);
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write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
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write_tcr0(delta);
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write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
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return 0;
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}
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static unsigned long ticks_per_jiffy;
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static void iop_set_mode(enum clock_event_mode mode,
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struct clock_event_device *unused)
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{
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u32 tmr = read_tmr0();
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switch (mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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write_tmr0(tmr & ~IOP_TMR_EN);
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write_tcr0(ticks_per_jiffy - 1);
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write_trr0(ticks_per_jiffy - 1);
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tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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/* ->set_next_event sets period and enables timer */
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tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
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break;
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case CLOCK_EVT_MODE_RESUME:
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tmr |= IOP_TMR_EN;
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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default:
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tmr &= ~IOP_TMR_EN;
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break;
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}
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write_tmr0(tmr);
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}
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static struct clock_event_device iop_clockevent = {
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.name = "iop_timer0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.rating = 300,
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.set_next_event = iop_set_next_event,
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.set_mode = iop_set_mode,
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};
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static irqreturn_t
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iop_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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write_tisr(1);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction iop_timer_irq = {
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.name = "IOP Timer Tick",
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.handler = iop_timer_interrupt,
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.dev_id = &iop_clockevent,
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};
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static unsigned long iop_tick_rate;
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unsigned long get_iop_tick_rate(void)
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{
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return iop_tick_rate;
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}
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EXPORT_SYMBOL(get_iop_tick_rate);
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void __init iop_init_time(unsigned long tick_rate)
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{
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u32 timer_ctl;
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setup_sched_clock(iop_read_sched_clock, 32, tick_rate);
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ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
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iop_tick_rate = tick_rate;
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timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
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IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
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/*
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* Set up interrupting clockevent timer 0.
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*/
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write_tmr0(timer_ctl & ~IOP_TMR_EN);
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write_tisr(1);
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setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
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iop_clockevent.cpumask = cpumask_of(0);
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clockevents_config_and_register(&iop_clockevent, tick_rate,
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0xf, 0xfffffffe);
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/*
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* Set up free-running clocksource timer 1.
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*/
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write_trr1(0xffffffff);
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write_tcr1(0xffffffff);
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write_tmr1(timer_ctl);
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clocksource_register_hz(&iop_clocksource, tick_rate);
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}
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