157 lines
4.6 KiB
C
157 lines
4.6 KiB
C
/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef UFS_QCOM_PHY_I_H_
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#define UFS_QCOM_PHY_I_H_
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/phy/phy-qcom-ufs.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
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({ \
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ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
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might_sleep_if(timeout_us); \
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for (;;) { \
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(val) = readl(addr); \
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if (cond) \
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break; \
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if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
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(val) = readl(addr); \
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break; \
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} \
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if (sleep_us) \
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usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
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} \
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(cond) ? 0 : -ETIMEDOUT; \
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})
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#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
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{ \
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.reg_offset = reg, \
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.cfg_value = val, \
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}
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#define UFS_QCOM_PHY_NAME_LEN 30
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enum {
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MASK_SERDES_START = 0x1,
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MASK_PCS_READY = 0x1,
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};
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enum {
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OFFSET_SERDES_START = 0x0,
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};
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struct ufs_qcom_phy_stored_attributes {
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u32 att;
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u32 value;
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};
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struct ufs_qcom_phy_calibration {
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u32 reg_offset;
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u32 cfg_value;
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};
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struct ufs_qcom_phy_vreg {
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const char *name;
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struct regulator *reg;
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int max_uA;
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int min_uV;
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int max_uV;
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bool enabled;
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};
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struct ufs_qcom_phy {
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struct list_head list;
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struct device *dev;
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void __iomem *mmio;
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void __iomem *dev_ref_clk_ctrl_mmio;
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struct clk *tx_iface_clk;
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struct clk *rx_iface_clk;
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bool is_iface_clk_enabled;
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struct clk *ref_clk_src;
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struct clk *ref_clk_parent;
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struct clk *ref_clk;
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bool is_ref_clk_enabled;
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bool is_dev_ref_clk_enabled;
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struct ufs_qcom_phy_vreg vdda_pll;
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struct ufs_qcom_phy_vreg vdda_phy;
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struct ufs_qcom_phy_vreg vddp_ref_clk;
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unsigned int quirks;
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/*
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* If UFS link is put into Hibern8 and if UFS PHY analog hardware is
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* power collapsed (by clearing UFS_PHY_POWER_DOWN_CONTROL), Hibern8
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* exit might fail even after powering on UFS PHY analog hardware.
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* Enabling this quirk will help to solve above issue by doing
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* custom PHY settings just before PHY analog power collapse.
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*/
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#define UFS_QCOM_PHY_QUIRK_HIBERN8_EXIT_AFTER_PHY_PWR_COLLAPSE BIT(0)
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u8 host_ctrl_rev_major;
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u16 host_ctrl_rev_minor;
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u16 host_ctrl_rev_step;
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char name[UFS_QCOM_PHY_NAME_LEN];
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struct ufs_qcom_phy_calibration *cached_regs;
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int cached_regs_table_size;
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bool is_powered_on;
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bool is_started;
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struct ufs_qcom_phy_specific_ops *phy_spec_ops;
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enum phy_mode mode;
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};
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/**
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* struct ufs_qcom_phy_specific_ops - set of pointers to functions which have a
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* specific implementation per phy. Each UFS phy, should implement
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* those functions according to its spec and requirements
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* @start_serdes: pointer to a function that starts the serdes
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* @is_physical_coding_sublayer_ready: pointer to a function that
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* checks pcs readiness. returns 0 for success and non-zero for error.
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* @set_tx_lane_enable: pointer to a function that enable tx lanes
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* @power_control: pointer to a function that controls analog rail of phy
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* and writes to QSERDES_RX_SIGDET_CNTRL attribute
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*/
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struct ufs_qcom_phy_specific_ops {
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void (*start_serdes)(struct ufs_qcom_phy *phy);
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int (*is_physical_coding_sublayer_ready)(struct ufs_qcom_phy *phy);
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void (*set_tx_lane_enable)(struct ufs_qcom_phy *phy, u32 val);
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void (*power_control)(struct ufs_qcom_phy *phy, bool val);
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};
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struct ufs_qcom_phy *get_ufs_qcom_phy(struct phy *generic_phy);
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int ufs_qcom_phy_power_on(struct phy *generic_phy);
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int ufs_qcom_phy_power_off(struct phy *generic_phy);
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int ufs_qcom_phy_init_clks(struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_init_vregulators(struct ufs_qcom_phy *phy_common);
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int ufs_qcom_phy_remove(struct phy *generic_phy,
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struct ufs_qcom_phy *ufs_qcom_phy);
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struct phy *ufs_qcom_phy_generic_probe(struct platform_device *pdev,
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struct ufs_qcom_phy *common_cfg,
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const struct phy_ops *ufs_qcom_phy_gen_ops,
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struct ufs_qcom_phy_specific_ops *phy_spec_ops);
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int ufs_qcom_phy_calibrate(struct ufs_qcom_phy *ufs_qcom_phy,
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struct ufs_qcom_phy_calibration *tbl_A, int tbl_size_A,
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struct ufs_qcom_phy_calibration *tbl_B, int tbl_size_B,
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bool is_rate_B);
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#endif
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