411 lines
11 KiB
C
411 lines
11 KiB
C
/*
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* Aic94xx SAS/SATA driver hardware interface header file.
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*
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* Copyright (C) 2005 Adaptec, Inc. All rights reserved.
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* Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
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*
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* This file is licensed under GPLv2.
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*
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* This file is part of the aic94xx driver.
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*
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* The aic94xx driver is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the
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* License.
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*
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* The aic94xx driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with the aic94xx driver; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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*/
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#ifndef _AIC94XX_HWI_H_
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#define _AIC94XX_HWI_H_
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <scsi/libsas.h>
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#include "aic94xx.h"
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#include "aic94xx_sas.h"
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/* Define ASD_MAX_PHYS to the maximum phys ever. Currently 8. */
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#define ASD_MAX_PHYS 8
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#define ASD_PCBA_SN_SIZE 12
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/* Those are to be further named properly, the "RAZORx" part, and
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* subsequently included in include/linux/pci_ids.h.
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*/
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR10 0x410
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR12 0x412
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR1E 0x41E
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR1F 0x41F
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR30 0x430
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR32 0x432
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR3E 0x43E
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#define PCI_DEVICE_ID_ADAPTEC2_RAZOR3F 0x43F
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struct asd_ha_addrspace {
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void __iomem *addr;
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unsigned long start; /* pci resource start */
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unsigned long len; /* pci resource len */
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unsigned long flags; /* pci resource flags */
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/* addresses internal to the host adapter */
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u32 swa_base; /* mmspace 1 (MBAR1) uses this only */
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u32 swb_base;
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u32 swc_base;
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};
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struct bios_struct {
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int present;
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u8 maj;
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u8 min;
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u32 bld;
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};
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struct unit_element_struct {
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u16 num;
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u16 size;
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void *area;
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};
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struct flash_struct {
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u32 bar;
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int present;
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int wide;
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u8 manuf;
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u8 dev_id;
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u8 sec_prot;
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u32 dir_offs;
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};
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struct asd_phy_desc {
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/* From CTRL-A settings, then set to what is appropriate */
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u8 sas_addr[SAS_ADDR_SIZE];
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u8 max_sas_lrate;
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u8 min_sas_lrate;
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u8 max_sata_lrate;
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u8 min_sata_lrate;
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u8 flags;
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#define ASD_CRC_DIS 1
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#define ASD_SATA_SPINUP_HOLD 2
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u8 phy_control_0; /* mode 5 reg 0x160 */
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u8 phy_control_1; /* mode 5 reg 0x161 */
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u8 phy_control_2; /* mode 5 reg 0x162 */
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u8 phy_control_3; /* mode 5 reg 0x163 */
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};
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struct asd_dma_tok {
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void *vaddr;
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dma_addr_t dma_handle;
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size_t size;
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};
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struct hw_profile {
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struct bios_struct bios;
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struct unit_element_struct ue;
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struct flash_struct flash;
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u8 sas_addr[SAS_ADDR_SIZE];
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char pcba_sn[ASD_PCBA_SN_SIZE+1];
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u8 enabled_phys; /* mask of enabled phys */
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struct asd_phy_desc phy_desc[ASD_MAX_PHYS];
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u32 max_scbs; /* absolute sequencer scb queue size */
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struct asd_dma_tok *scb_ext;
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u32 max_ddbs;
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struct asd_dma_tok *ddb_ext;
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spinlock_t ddb_lock;
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void *ddb_bitmap;
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int num_phys; /* ENABLEABLE */
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int max_phys; /* REPORTED + ENABLEABLE */
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unsigned addr_range; /* max # of addrs; max # of possible ports */
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unsigned port_name_base;
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unsigned dev_name_base;
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unsigned sata_name_base;
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};
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struct asd_ascb {
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struct list_head list;
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struct asd_ha_struct *ha;
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struct scb *scb; /* equals dma_scb->vaddr */
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struct asd_dma_tok dma_scb;
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struct asd_dma_tok *sg_arr;
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void (*tasklet_complete)(struct asd_ascb *, struct done_list_struct *);
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u8 uldd_timer:1;
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/* internally generated command */
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struct timer_list timer;
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struct completion completion;
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u8 tag_valid:1;
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__be16 tag; /* error recovery only */
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/* If this is an Empty SCB, index of first edb in seq->edb_arr. */
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int edb_index;
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/* Used by the timer timeout function. */
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int tc_index;
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void *uldd_task;
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};
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#define ASD_DL_SIZE_BITS 0x8
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#define ASD_DL_SIZE (1<<(2+ASD_DL_SIZE_BITS))
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#define ASD_DEF_DL_TOGGLE 0x01
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struct asd_seq_data {
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spinlock_t pend_q_lock;
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u16 scbpro;
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int pending;
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struct list_head pend_q;
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int can_queue; /* per adapter */
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struct asd_dma_tok next_scb; /* next scb to be delivered to CSEQ */
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spinlock_t tc_index_lock;
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void **tc_index_array;
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void *tc_index_bitmap;
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int tc_index_bitmap_bits;
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struct tasklet_struct dl_tasklet;
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struct done_list_struct *dl; /* array of done list entries, equals */
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struct asd_dma_tok *actual_dl; /* actual_dl->vaddr */
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int dl_toggle;
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int dl_next;
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int num_edbs;
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struct asd_dma_tok **edb_arr;
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int num_escbs;
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struct asd_ascb **escb_arr; /* array of pointers to escbs */
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};
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/* This is an internal port structure. These are used to get accurate
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* phy_mask for updating DDB 0.
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*/
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struct asd_port {
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u8 sas_addr[SAS_ADDR_SIZE];
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u8 attached_sas_addr[SAS_ADDR_SIZE];
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u32 phy_mask;
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int num_phys;
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};
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/* This is the Host Adapter structure. It describes the hardware
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* SAS adapter.
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*/
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struct asd_ha_struct {
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struct pci_dev *pcidev;
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const char *name;
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struct sas_ha_struct sas_ha;
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u8 revision_id;
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int iospace;
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spinlock_t iolock;
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struct asd_ha_addrspace io_handle[2];
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struct hw_profile hw_prof;
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struct asd_phy phys[ASD_MAX_PHYS];
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spinlock_t asd_ports_lock;
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struct asd_port asd_ports[ASD_MAX_PHYS];
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struct asd_sas_port ports[ASD_MAX_PHYS];
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struct dma_pool *scb_pool;
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struct asd_seq_data seq; /* sequencer related */
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};
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/* ---------- Common macros ---------- */
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#define ASD_BUSADDR_LO(__dma_handle) ((u32)(__dma_handle))
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#define ASD_BUSADDR_HI(__dma_handle) (((sizeof(dma_addr_t))==8) \
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? ((u32)((__dma_handle) >> 32)) \
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: ((u32)0))
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#define dev_to_asd_ha(__dev) pci_get_drvdata(to_pci_dev(__dev))
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#define SCB_SITE_VALID(__site_no) (((__site_no) & 0xF0FF) != 0x00FF \
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&& ((__site_no) & 0xF0FF) > 0x001F)
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/* For each bit set in __lseq_mask, set __lseq to equal the bit
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* position of the set bit and execute the statement following.
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* __mc is the temporary mask, used as a mask "counter".
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*/
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#define for_each_sequencer(__lseq_mask, __mc, __lseq) \
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for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
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if (((__mc) & 1))
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#define for_each_phy(__lseq_mask, __mc, __lseq) \
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for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
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if (((__mc) & 1))
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#define PHY_ENABLED(_HA, _I) ((_HA)->hw_prof.enabled_phys & (1<<(_I)))
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/* ---------- DMA allocs ---------- */
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static inline struct asd_dma_tok *asd_dmatok_alloc(gfp_t flags)
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{
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return kmem_cache_alloc(asd_dma_token_cache, flags);
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}
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static inline void asd_dmatok_free(struct asd_dma_tok *token)
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{
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kmem_cache_free(asd_dma_token_cache, token);
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}
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static inline struct asd_dma_tok *asd_alloc_coherent(struct asd_ha_struct *
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asd_ha, size_t size,
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gfp_t flags)
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{
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struct asd_dma_tok *token = asd_dmatok_alloc(flags);
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if (token) {
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token->size = size;
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token->vaddr = dma_alloc_coherent(&asd_ha->pcidev->dev,
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token->size,
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&token->dma_handle,
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flags);
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if (!token->vaddr) {
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asd_dmatok_free(token);
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token = NULL;
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}
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}
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return token;
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}
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static inline void asd_free_coherent(struct asd_ha_struct *asd_ha,
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struct asd_dma_tok *token)
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{
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if (token) {
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dma_free_coherent(&asd_ha->pcidev->dev, token->size,
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token->vaddr, token->dma_handle);
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asd_dmatok_free(token);
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}
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}
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static inline void asd_init_ascb(struct asd_ha_struct *asd_ha,
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struct asd_ascb *ascb)
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{
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INIT_LIST_HEAD(&ascb->list);
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ascb->scb = ascb->dma_scb.vaddr;
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ascb->ha = asd_ha;
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ascb->timer.function = NULL;
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init_timer(&ascb->timer);
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ascb->tc_index = -1;
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init_completion(&ascb->completion);
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}
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/* Must be called with the tc_index_lock held!
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*/
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static inline void asd_tc_index_release(struct asd_seq_data *seq, int index)
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{
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seq->tc_index_array[index] = NULL;
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clear_bit(index, seq->tc_index_bitmap);
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}
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/* Must be called with the tc_index_lock held!
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*/
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static inline int asd_tc_index_get(struct asd_seq_data *seq, void *ptr)
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{
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int index;
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index = find_first_zero_bit(seq->tc_index_bitmap,
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seq->tc_index_bitmap_bits);
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if (index == seq->tc_index_bitmap_bits)
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return -1;
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seq->tc_index_array[index] = ptr;
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set_bit(index, seq->tc_index_bitmap);
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return index;
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}
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/* Must be called with the tc_index_lock held!
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*/
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static inline void *asd_tc_index_find(struct asd_seq_data *seq, int index)
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{
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return seq->tc_index_array[index];
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}
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/**
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* asd_ascb_free -- free a single aSCB after is has completed
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* @ascb: pointer to the aSCB of interest
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*
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* This frees an aSCB after it has been executed/completed by
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* the sequencer.
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*/
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static inline void asd_ascb_free(struct asd_ascb *ascb)
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{
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if (ascb) {
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struct asd_ha_struct *asd_ha = ascb->ha;
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unsigned long flags;
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BUG_ON(!list_empty(&ascb->list));
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spin_lock_irqsave(&ascb->ha->seq.tc_index_lock, flags);
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asd_tc_index_release(&ascb->ha->seq, ascb->tc_index);
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spin_unlock_irqrestore(&ascb->ha->seq.tc_index_lock, flags);
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dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
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ascb->dma_scb.dma_handle);
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kmem_cache_free(asd_ascb_cache, ascb);
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}
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}
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/**
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* asd_ascb_list_free -- free a list of ascbs
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* @ascb_list: a list of ascbs
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*
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* This function will free a list of ascbs allocated by asd_ascb_alloc_list.
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* It is used when say the scb queueing function returned QUEUE_FULL,
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* and we do not need the ascbs any more.
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*/
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static inline void asd_ascb_free_list(struct asd_ascb *ascb_list)
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{
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LIST_HEAD(list);
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struct list_head *n, *pos;
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__list_add(&list, ascb_list->list.prev, &ascb_list->list);
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list_for_each_safe(pos, n, &list) {
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list_del_init(pos);
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asd_ascb_free(list_entry(pos, struct asd_ascb, list));
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}
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}
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/* ---------- Function declarations ---------- */
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int asd_init_hw(struct asd_ha_struct *asd_ha);
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irqreturn_t asd_hw_isr(int irq, void *dev_id);
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struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
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*asd_ha, int *num,
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gfp_t gfp_mask);
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int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
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int num);
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int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
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int num);
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int asd_init_post_escbs(struct asd_ha_struct *asd_ha);
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void asd_build_control_phy(struct asd_ascb *ascb, int phy_id, u8 subfunc);
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void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
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void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
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int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask);
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void asd_build_initiate_link_adm_task(struct asd_ascb *ascb, int phy_id,
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u8 subfunc);
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void asd_ascb_timedout(unsigned long data);
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int asd_chip_hardrst(struct asd_ha_struct *asd_ha);
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#endif
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