335 lines
8.3 KiB
C
335 lines
8.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Code to handle x86 style IRQs plus some generic interrupt stuff.
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*
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* Copyright (C) 1992 Linus Torvalds
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* Copyright (C) 1994 - 2000 Ralf Baechle
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*/
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/sysdev.h>
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#include <asm/i8259.h>
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#include <asm/io.h>
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void enable_8259A_irq(unsigned int irq);
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void disable_8259A_irq(unsigned int irq);
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/*
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* This is the 'legacy' 8259A Programmable Interrupt Controller,
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* present in the majority of PC/AT boxes.
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* plus some generic x86 specific things if generic specifics makes
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* any sense at all.
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* this file should become arch/i386/kernel/irq.c when the old irq.c
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* moves to arch independent land
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*/
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DEFINE_SPINLOCK(i8259A_lock);
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static void end_8259A_irq (unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
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irq_desc[irq].action)
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enable_8259A_irq(irq);
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}
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#define shutdown_8259A_irq disable_8259A_irq
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void mask_and_ack_8259A(unsigned int);
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static unsigned int startup_8259A_irq(unsigned int irq)
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{
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enable_8259A_irq(irq);
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return 0; /* never anything pending */
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}
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static struct irq_chip i8259A_irq_type = {
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.typename = "XT-PIC",
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.startup = startup_8259A_irq,
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.shutdown = shutdown_8259A_irq,
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.enable = enable_8259A_irq,
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.disable = disable_8259A_irq,
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.ack = mask_and_ack_8259A,
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.end = end_8259A_irq,
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};
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/*
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* 8259A PIC functions to handle ISA devices:
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*/
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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static unsigned int cached_irq_mask = 0xffff;
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#define cached_21 (cached_irq_mask)
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#define cached_A1 (cached_irq_mask >> 8)
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void disable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask |= mask;
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if (irq & 8)
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outb(cached_A1,0xA1);
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else
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outb(cached_21,0x21);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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void enable_8259A_irq(unsigned int irq)
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{
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unsigned int mask = ~(1 << irq);
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask &= mask;
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if (irq & 8)
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outb(cached_A1,0xA1);
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else
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outb(cached_21,0x21);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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int i8259A_irq_pending(unsigned int irq)
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{
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unsigned int mask = 1 << irq;
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unsigned long flags;
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int ret;
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spin_lock_irqsave(&i8259A_lock, flags);
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if (irq < 8)
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ret = inb(0x20) & mask;
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else
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ret = inb(0xA0) & (mask >> 8);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return ret;
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}
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void make_8259A_irq(unsigned int irq)
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{
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disable_irq_nosync(irq);
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irq_desc[irq].chip = &i8259A_irq_type;
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enable_irq(irq);
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}
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/*
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* This function assumes to be called rarely. Switching between
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* 8259A registers is slow.
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* This has to be protected by the irq controller spinlock
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* before being called.
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*/
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static inline int i8259A_irq_real(unsigned int irq)
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{
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int value;
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int irqmask = 1 << irq;
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if (irq < 8) {
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outb(0x0B,0x20); /* ISR register */
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value = inb(0x20) & irqmask;
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outb(0x0A,0x20); /* back to the IRR register */
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return value;
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}
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outb(0x0B,0xA0); /* ISR register */
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value = inb(0xA0) & (irqmask >> 8);
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outb(0x0A,0xA0); /* back to the IRR register */
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return value;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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void mask_and_ack_8259A(unsigned int irq)
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{
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unsigned int irqmask = 1 << irq;
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want to overdo
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* spurious IRQ handling - it's usually a sign of hardware problems, so
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* we only do the checks we can do without slowing down good hardware
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* nnecesserily.
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*
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* Note that IRQ7 and IRQ15 (the two spurious IRQs usually resulting
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* rom the 8259A-1|2 PICs) occur even if the IRQ is masked in the 8259A.
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* Thus we can check spurious 8259A IRQs without doing the quite slow
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* i8259A_irq_real() call for every IRQ. This does not cover 100% of
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* spurious interrupts, but should be enough to warn the user that
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* there is something bad going on ...
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*/
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if (cached_irq_mask & irqmask)
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goto spurious_8259A_irq;
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cached_irq_mask |= irqmask;
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handle_real_irq:
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if (irq & 8) {
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inb(0xA1); /* DUMMY - (do we need this?) */
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outb(cached_A1,0xA1);
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outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
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outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
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} else {
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inb(0x21); /* DUMMY - (do we need this?) */
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outb(cached_21,0x21);
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outb(0x60+irq,0x20); /* 'Specific EOI' to master */
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}
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#ifdef CONFIG_MIPS_MT_SMTC
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if (irq_hwmask[irq] & ST0_IM)
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set_c0_status(irq_hwmask[irq] & ST0_IM);
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#endif /* CONFIG_MIPS_MT_SMTC */
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spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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/*
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* this is the slow path - should happen rarely.
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*/
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if (i8259A_irq_real(irq))
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/*
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* oops, the IRQ _is_ in service according to the
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* 8259A - not spurious, go handle it.
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*/
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goto handle_real_irq;
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{
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static int spurious_irq_mask = 0;
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/*
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* At this point we can be sure the IRQ is spurious,
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* lets ACK and report it. [once per IRQ]
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*/
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if (!(spurious_irq_mask & irqmask)) {
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printk(KERN_DEBUG "spurious 8259A interrupt: IRQ%d.\n", irq);
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spurious_irq_mask |= irqmask;
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}
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atomic_inc(&irq_err_count);
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/*
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* Theoretically we do not have to handle this IRQ,
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* but in Linux this does not cause problems and is
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* simpler for us.
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*/
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goto handle_real_irq;
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}
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}
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static int i8259A_resume(struct sys_device *dev)
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{
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init_8259A(0);
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return 0;
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}
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static struct sysdev_class i8259_sysdev_class = {
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set_kset_name("i8259"),
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.resume = i8259A_resume,
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};
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static struct sys_device device_i8259A = {
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.id = 0,
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.cls = &i8259_sysdev_class,
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};
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static int __init i8259A_init_sysfs(void)
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{
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int error = sysdev_class_register(&i8259_sysdev_class);
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if (!error)
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error = sysdev_register(&device_i8259A);
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return error;
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}
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device_initcall(i8259A_init_sysfs);
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void __init init_8259A(int auto_eoi)
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{
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unsigned long flags;
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spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, 0x21); /* mask all of 8259A-1 */
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outb(0xff, 0xA1); /* mask all of 8259A-2 */
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/*
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* outb_p - this has to work on a wide range of PC hardware.
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*/
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outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
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outb_p(0x00, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x00-0x07 */
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outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
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if (auto_eoi)
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outb_p(0x03, 0x21); /* master does Auto EOI */
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else
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outb_p(0x01, 0x21); /* master expects normal EOI */
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outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
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outb_p(0x08, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x08-0x0f */
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outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
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outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
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is to be investigated) */
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if (auto_eoi)
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/*
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* in AEOI mode we just have to mask the interrupt
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* when acking.
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*/
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i8259A_irq_type.ack = disable_8259A_irq;
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else
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i8259A_irq_type.ack = mask_and_ack_8259A;
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udelay(100); /* wait for 8259A to initialize */
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outb(cached_21, 0x21); /* restore master IRQ mask */
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outb(cached_A1, 0xA1); /* restore slave IRQ mask */
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spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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/*
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* IRQ2 is cascade interrupt to second interrupt controller
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*/
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static struct irqaction irq2 = {
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no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL
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};
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static struct resource pic1_io_resource = {
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.name = "pic1", .start = 0x20, .end = 0x3f, .flags = IORESOURCE_BUSY
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};
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static struct resource pic2_io_resource = {
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.name = "pic2", .start = 0xa0, .end = 0xbf, .flags = IORESOURCE_BUSY
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};
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/*
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* On systems with i8259-style interrupt controllers we assume for
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* driver compatibility reasons interrupts 0 - 15 to be the i8259
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* interrupts even if the hardware uses a different interrupt numbering.
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*/
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void __init init_i8259_irqs (void)
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{
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int i;
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request_resource(&ioport_resource, &pic1_io_resource);
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request_resource(&ioport_resource, &pic2_io_resource);
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init_8259A(0);
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for (i = 0; i < 16; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].chip = &i8259A_irq_type;
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}
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setup_irq(2, &irq2);
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}
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