110 lines
3.7 KiB
C
110 lines
3.7 KiB
C
/*
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _ALPHASCALE_ASM9260_ICOLL_H
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#define _ALPHASCALE_ASM9260_ICOLL_H
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#define ASM9260_NUM_IRQS 64
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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* 0x4 - set mode, OR logic.
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* 0x8 - clr mode, XOR logic.
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* 0xc - togle mode.
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*/
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#define ASM9260_HW_ICOLL_VECTOR 0x0000
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/*
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* bits 31:2
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* This register presents the vector address for the interrupt currently
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* active on the CPU IRQ input. Writing to this register notifies the
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* interrupt collector that the interrupt service routine for the current
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* interrupt has been entered.
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* The exception trap should have a LDPC instruction from this address:
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* LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018
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*/
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/*
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* The Interrupt Collector Level Acknowledge Register is used by software to
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* indicate the completion of an interrupt on a specific level.
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* This register is written at the very end of an interrupt service routine. If
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* nesting is used then the CPU irq must be turned on before writing to this
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* register to avoid a race condition in the CPU interrupt hardware.
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*/
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#define ASM9260_HW_ICOLL_LEVELACK 0x0010
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#define ASM9260_BM_LEVELn(nr) BIT(nr)
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#define ASM9260_HW_ICOLL_CTRL 0x0020
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/*
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* ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on
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* asm9260.
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*/
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#define ASM9260_BM_CTRL_SFTRST BIT(31)
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#define ASM9260_BM_CTRL_CLKGATE BIT(30)
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/* disable interrupt level nesting */
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#define ASM9260_BM_CTRL_NO_NESTING BIT(19)
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/*
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* Set this bit to one enable the RISC32-style read side effect associated with
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* the vector address register. In this mode, interrupt in-service is signaled
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* by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt
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* vector address. Set this bit to zero for normal operation, in which the ISR
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* signals in-service explicitly by means of a write to the
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* ASM9260_HW_ICOLL_VECTOR register.
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* 0 - Must Write to Vector register to go in-service.
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* 1 - Go in-service as a read side effect
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*/
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#define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18)
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#define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16)
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#define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030
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/*
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* bits 5:0
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* Vector number of current interrupt. Multiply by 4 and add to vector base
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* address to obtain the value in ASM9260_HW_ICOLL_VECTOR.
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*/
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/*
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* RAW0 and RAW1 provides a read-only view of the raw interrupt request lines
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* coming from various parts of the chip. Its purpose is to improve diagnostic
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* observability.
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*/
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#define ASM9260_HW_ICOLL_RAW0 0x0040
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#define ASM9260_HW_ICOLL_RAW1 0x0050
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#define ASM9260_HW_ICOLL_INTERRUPT0 0x0060
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#define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10)
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/*
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* WARNING: Modifying the priority of an enabled interrupt may result in
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* undefined behavior.
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*/
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#define ASM9260_BM_INT_PRIORITY_MASK 0x3
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#define ASM9260_BM_INT_ENABLE BIT(2)
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#define ASM9260_BM_INT_SOFTIRQ BIT(3)
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#define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3)
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#define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \
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ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)))
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#define ASM9260_HW_ICOLL_VBASE 0x0160
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/*
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* bits 31:2
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* This bitfield holds the upper 30 bits of the base address of the vector
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* table.
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*/
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#define ASM9260_HW_ICOLL_CLEAR0 0x01d0
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#define ASM9260_HW_ICOLL_CLEAR1 0x01e0
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#define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \
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+ SET_REG)
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#define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f)
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/* Scratchpad */
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#define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0
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#endif
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