144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/sched_clock.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/time.h>
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#include "soc.h"
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#include "platform.h"
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/*************************************************************************
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* Timer handling for EP93xx
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*************************************************************************
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* The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
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* 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
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* an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
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* is free-running, and can't generate interrupts.
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*
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* The 508 kHz timers are ideal for use for the timer interrupt, as the
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* most common values of HZ divide 508 kHz nicely. We pick the 32 bit
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* timer (timer 3) to get as long sleep intervals as possible when using
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* CONFIG_NO_HZ.
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*
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* The higher clock rate of timer 4 makes it a better choice than the
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* other timers for use as clock source and for sched_clock(), providing
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* a stable 40 bit time base.
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*************************************************************************
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*/
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#define EP93XX_TIMER_REG(x) (EP93XX_TIMER_BASE + (x))
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#define EP93XX_TIMER1_LOAD EP93XX_TIMER_REG(0x00)
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#define EP93XX_TIMER1_VALUE EP93XX_TIMER_REG(0x04)
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#define EP93XX_TIMER1_CONTROL EP93XX_TIMER_REG(0x08)
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#define EP93XX_TIMER123_CONTROL_ENABLE (1 << 7)
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#define EP93XX_TIMER123_CONTROL_MODE (1 << 6)
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#define EP93XX_TIMER123_CONTROL_CLKSEL (1 << 3)
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#define EP93XX_TIMER1_CLEAR EP93XX_TIMER_REG(0x0c)
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#define EP93XX_TIMER2_LOAD EP93XX_TIMER_REG(0x20)
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#define EP93XX_TIMER2_VALUE EP93XX_TIMER_REG(0x24)
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#define EP93XX_TIMER2_CONTROL EP93XX_TIMER_REG(0x28)
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#define EP93XX_TIMER2_CLEAR EP93XX_TIMER_REG(0x2c)
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#define EP93XX_TIMER4_VALUE_LOW EP93XX_TIMER_REG(0x60)
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#define EP93XX_TIMER4_VALUE_HIGH EP93XX_TIMER_REG(0x64)
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#define EP93XX_TIMER4_VALUE_HIGH_ENABLE (1 << 8)
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#define EP93XX_TIMER3_LOAD EP93XX_TIMER_REG(0x80)
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#define EP93XX_TIMER3_VALUE EP93XX_TIMER_REG(0x84)
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#define EP93XX_TIMER3_CONTROL EP93XX_TIMER_REG(0x88)
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#define EP93XX_TIMER3_CLEAR EP93XX_TIMER_REG(0x8c)
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#define EP93XX_TIMER123_RATE 508469
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#define EP93XX_TIMER4_RATE 983040
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static u64 notrace ep93xx_read_sched_clock(void)
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{
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u64 ret;
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ret = readl(EP93XX_TIMER4_VALUE_LOW);
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ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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return ret;
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}
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static u64 ep93xx_clocksource_read(struct clocksource *c)
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{
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u64 ret;
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ret = readl(EP93XX_TIMER4_VALUE_LOW);
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ret |= ((u64) (readl(EP93XX_TIMER4_VALUE_HIGH) & 0xff) << 32);
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return (u64) ret;
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}
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static int ep93xx_clkevt_set_next_event(unsigned long next,
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struct clock_event_device *evt)
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{
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/* Default mode: periodic, off, 508 kHz */
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u32 tmode = EP93XX_TIMER123_CONTROL_MODE |
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EP93XX_TIMER123_CONTROL_CLKSEL;
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/* Clear timer */
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writel(tmode, EP93XX_TIMER3_CONTROL);
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/* Set next event */
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writel(next, EP93XX_TIMER3_LOAD);
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writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE,
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EP93XX_TIMER3_CONTROL);
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return 0;
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}
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static int ep93xx_clkevt_shutdown(struct clock_event_device *evt)
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{
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/* Disable timer */
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writel(0, EP93XX_TIMER3_CONTROL);
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return 0;
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}
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static struct clock_event_device ep93xx_clockevent = {
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.name = "timer1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = ep93xx_clkevt_shutdown,
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.set_state_oneshot = ep93xx_clkevt_shutdown,
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.tick_resume = ep93xx_clkevt_shutdown,
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.set_next_event = ep93xx_clkevt_set_next_event,
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.rating = 300,
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};
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static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* Writing any value clears the timer interrupt */
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writel(1, EP93XX_TIMER3_CLEAR);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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void __init ep93xx_timer_init(void)
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{
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int irq = IRQ_EP93XX_TIMER3;
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unsigned long flags = IRQF_TIMER | IRQF_IRQPOLL;
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/* Enable and register clocksource and sched_clock on timer 4 */
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writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE,
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EP93XX_TIMER4_VALUE_HIGH);
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clocksource_mmio_init(NULL, "timer4",
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EP93XX_TIMER4_RATE, 200, 40,
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ep93xx_clocksource_read);
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sched_clock_register(ep93xx_read_sched_clock, 40,
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EP93XX_TIMER4_RATE);
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/* Set up clockevent on timer 3 */
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if (request_irq(irq, ep93xx_timer_interrupt, flags, "ep93xx timer",
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&ep93xx_clockevent))
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pr_err("Failed to request irq %d (ep93xx timer)\n", irq);
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clockevents_config_and_register(&ep93xx_clockevent,
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EP93XX_TIMER123_RATE,
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1,
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0xffffffffU);
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}
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