247 lines
8.0 KiB
C
247 lines
8.0 KiB
C
/*
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* linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
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*
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* Copyright (C) 2005 ARM Ltd
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* Copyright (C) 2010 ST-Ericsson SA
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* pl08x information required by platform code
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*
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* Please credit ARM.com
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* Documentation: ARM DDI 0196D
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*/
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#ifndef AMBA_PL08X_H
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#define AMBA_PL08X_H
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/* We need sizes of structs from this header */
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#include <linux/dmaengine.h>
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#include <linux/interrupt.h>
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struct pl08x_lli;
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struct pl08x_driver_data;
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/* Bitmasks for selecting AHB ports for DMA transfers */
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enum {
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PL08X_AHB1 = (1 << 0),
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PL08X_AHB2 = (1 << 1)
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};
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/**
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* struct pl08x_channel_data - data structure to pass info between
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* platform and PL08x driver regarding channel configuration
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* @bus_id: name of this device channel, not just a device name since
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* devices may have more than one channel e.g. "foo_tx"
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* @min_signal: the minimum DMA signal number to be muxed in for this
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* channel (for platforms supporting muxed signals). If you have
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* static assignments, make sure this is set to the assigned signal
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* number, PL08x have 16 possible signals in number 0 thru 15 so
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* when these are not enough they often get muxed (in hardware)
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* disabling simultaneous use of the same channel for two devices.
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* @max_signal: the maximum DMA signal number to be muxed in for
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* the channel. Set to the same as min_signal for
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* devices with static assignments
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* @muxval: a number usually used to poke into some mux regiser to
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* mux in the signal to this channel
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* @cctl_opt: default options for the channel control register
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* @device_fc: Flow Controller Settings for ccfg register. Only valid for slave
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* channels. Fill with 'true' if peripheral should be flow controller. Direction
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* will be selected at Runtime.
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* @addr: source/target address in physical memory for this DMA channel,
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* can be the address of a FIFO register for burst requests for example.
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* This can be left undefined if the PrimeCell API is used for configuring
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* this.
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* @circular_buffer: whether the buffer passed in is circular and
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* shall simply be looped round round (like a record baby round
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* round round round)
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* @single: the device connected to this channel will request single DMA
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* transfers, not bursts. (Bursts are default.)
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* @periph_buses: the device connected to this channel is accessible via
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* these buses (use PL08X_AHB1 | PL08X_AHB2).
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*/
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struct pl08x_channel_data {
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char *bus_id;
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int min_signal;
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int max_signal;
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u32 muxval;
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u32 cctl;
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bool device_fc;
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dma_addr_t addr;
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bool circular_buffer;
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bool single;
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u8 periph_buses;
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};
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/**
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* Struct pl08x_bus_data - information of source or destination
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* busses for a transfer
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* @addr: current address
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* @maxwidth: the maximum width of a transfer on this bus
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* @buswidth: the width of this bus in bytes: 1, 2 or 4
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*/
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struct pl08x_bus_data {
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dma_addr_t addr;
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u8 maxwidth;
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u8 buswidth;
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};
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/**
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* struct pl08x_phy_chan - holder for the physical channels
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* @id: physical index to this channel
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* @lock: a lock to use when altering an instance of this struct
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* @signal: the physical signal (aka channel) serving this physical channel
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* right now
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* @serving: the virtual channel currently being served by this physical
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* channel
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*/
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struct pl08x_phy_chan {
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unsigned int id;
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void __iomem *base;
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spinlock_t lock;
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int signal;
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struct pl08x_dma_chan *serving;
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};
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/**
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* struct pl08x_sg - structure containing data per sg
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* @src_addr: src address of sg
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* @dst_addr: dst address of sg
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* @len: transfer len in bytes
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* @node: node for txd's dsg_list
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*/
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struct pl08x_sg {
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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size_t len;
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struct list_head node;
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};
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/**
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* struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
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* @tx: async tx descriptor
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* @node: node for txd list for channels
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* @dsg_list: list of children sg's
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* @direction: direction of transfer
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* @llis_bus: DMA memory address (physical) start for the LLIs
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* @llis_va: virtual memory address start for the LLIs
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* @cctl: control reg values for current txd
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* @ccfg: config reg values for current txd
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*/
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struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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struct list_head dsg_list;
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enum dma_data_direction direction;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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u32 cctl;
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/*
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* Settings to be put into the physical channel when we
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* trigger this txd. Other registers are in llis_va[0].
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*/
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u32 ccfg;
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};
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/**
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* struct pl08x_dma_chan_state - holds the PL08x specific virtual channel
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* states
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* @PL08X_CHAN_IDLE: the channel is idle
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* @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
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* channel and is running a transfer on it
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* @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
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* channel, but the transfer is currently paused
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* @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
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* channel to become available (only pertains to memcpy channels)
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*/
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enum pl08x_dma_chan_state {
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PL08X_CHAN_IDLE,
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PL08X_CHAN_RUNNING,
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PL08X_CHAN_PAUSED,
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PL08X_CHAN_WAITING,
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};
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/**
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* struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
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* @chan: wrappped abstract channel
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* @phychan: the physical channel utilized by this channel, if there is one
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* @phychan_hold: if non-zero, hold on to the physical channel even if we
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* have no pending entries
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* @tasklet: tasklet scheduled by the IRQ to handle actual work etc
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* @name: name of channel
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* @cd: channel platform data
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* @runtime_addr: address for RX/TX according to the runtime config
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* @runtime_direction: current direction of this channel according to
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* runtime config
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* @lc: last completed transaction on this channel
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* @pend_list: queued transactions pending on this channel
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* @at: active transaction on this channel
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* @lock: a lock for this channel data
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* @host: a pointer to the host (internal use)
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* @state: whether the channel is idle, paused, running etc
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* @slave: whether this channel is a device (slave) or for memcpy
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* @waiting: a TX descriptor on this channel which is waiting for a physical
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* channel to become available
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*/
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struct pl08x_dma_chan {
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struct dma_chan chan;
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struct pl08x_phy_chan *phychan;
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int phychan_hold;
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struct tasklet_struct tasklet;
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char *name;
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const struct pl08x_channel_data *cd;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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u32 src_cctl;
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u32 dst_cctl;
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enum dma_data_direction runtime_direction;
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dma_cookie_t lc;
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struct list_head pend_list;
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struct pl08x_txd *at;
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spinlock_t lock;
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struct pl08x_driver_data *host;
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enum pl08x_dma_chan_state state;
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bool slave;
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struct pl08x_txd *waiting;
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};
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/**
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* struct pl08x_platform_data - the platform configuration for the PL08x
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* PrimeCells.
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* @slave_channels: the channels defined for the different devices on the
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* platform, all inclusive, including multiplexed channels. The available
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* physical channels will be multiplexed around these signals as they are
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* requested, just enumerate all possible channels.
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* @get_signal: request a physical signal to be used for a DMA transfer
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* immediately: if there is some multiplexing or similar blocking the use
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* of the channel the transfer can be denied by returning less than zero,
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* else it returns the allocated signal number
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* @put_signal: indicate to the platform that this physical signal is not
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* running any DMA transfer and multiplexing can be recycled
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* @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2
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* @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2
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*/
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struct pl08x_platform_data {
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const struct pl08x_channel_data *slave_channels;
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unsigned int num_slave_channels;
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struct pl08x_channel_data memcpy_channel;
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int (*get_signal)(struct pl08x_dma_chan *);
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void (*put_signal)(struct pl08x_dma_chan *);
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u8 lli_buses;
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u8 mem_buses;
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};
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#ifdef CONFIG_AMBA_PL08X
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bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
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#else
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static inline bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
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{
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return false;
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}
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#endif
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#endif /* AMBA_PL08X_H */
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