220 lines
5.6 KiB
C
220 lines
5.6 KiB
C
/*
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* Generic IEEE 1394 definitions
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*/
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#ifndef _IEEE1394_IEEE1394_H
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#define _IEEE1394_IEEE1394_H
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#define TCODE_WRITEQ 0x0
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#define TCODE_WRITEB 0x1
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#define TCODE_WRITE_RESPONSE 0x2
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#define TCODE_READQ 0x4
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#define TCODE_READB 0x5
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#define TCODE_READQ_RESPONSE 0x6
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#define TCODE_READB_RESPONSE 0x7
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#define TCODE_CYCLE_START 0x8
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#define TCODE_LOCK_REQUEST 0x9
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#define TCODE_ISO_DATA 0xa
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#define TCODE_STREAM_DATA 0xa
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#define TCODE_LOCK_RESPONSE 0xb
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#define RCODE_COMPLETE 0x0
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#define RCODE_CONFLICT_ERROR 0x4
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#define RCODE_DATA_ERROR 0x5
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#define RCODE_TYPE_ERROR 0x6
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#define RCODE_ADDRESS_ERROR 0x7
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#define EXTCODE_MASK_SWAP 0x1
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#define EXTCODE_COMPARE_SWAP 0x2
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#define EXTCODE_FETCH_ADD 0x3
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#define EXTCODE_LITTLE_ADD 0x4
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#define EXTCODE_BOUNDED_ADD 0x5
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#define EXTCODE_WRAP_ADD 0x6
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#define ACK_COMPLETE 0x1
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#define ACK_PENDING 0x2
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#define ACK_BUSY_X 0x4
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#define ACK_BUSY_A 0x5
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#define ACK_BUSY_B 0x6
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#define ACK_TARDY 0xb
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#define ACK_CONFLICT_ERROR 0xc
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#define ACK_DATA_ERROR 0xd
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#define ACK_TYPE_ERROR 0xe
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#define ACK_ADDRESS_ERROR 0xf
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/* Non-standard "ACK codes" for internal use */
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#define ACKX_NONE (-1)
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#define ACKX_SEND_ERROR (-2)
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#define ACKX_ABORTED (-3)
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#define ACKX_TIMEOUT (-4)
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#define IEEE1394_SPEED_100 0x00
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#define IEEE1394_SPEED_200 0x01
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#define IEEE1394_SPEED_400 0x02
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#define IEEE1394_SPEED_800 0x03
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#define IEEE1394_SPEED_1600 0x04
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#define IEEE1394_SPEED_3200 0x05
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/* The current highest tested speed supported by the subsystem */
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#define IEEE1394_SPEED_MAX IEEE1394_SPEED_800
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/* Maps speed values above to a string representation */
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extern const char *hpsb_speedto_str[];
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/* 1394a cable PHY packets */
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#define SELFID_PWRCL_NO_POWER 0x0
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#define SELFID_PWRCL_PROVIDE_15W 0x1
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#define SELFID_PWRCL_PROVIDE_30W 0x2
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#define SELFID_PWRCL_PROVIDE_45W 0x3
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#define SELFID_PWRCL_USE_1W 0x4
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#define SELFID_PWRCL_USE_3W 0x5
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#define SELFID_PWRCL_USE_6W 0x6
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#define SELFID_PWRCL_USE_10W 0x7
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#define SELFID_PORT_CHILD 0x3
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#define SELFID_PORT_PARENT 0x2
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#define SELFID_PORT_NCONN 0x1
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#define SELFID_PORT_NONE 0x0
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#define SELFID_SPEED_UNKNOWN 0x3 /* 1394b PHY */
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#define PHYPACKET_LINKON 0x40000000
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#define PHYPACKET_PHYCONFIG_R 0x00800000
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#define PHYPACKET_PHYCONFIG_T 0x00400000
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#define EXTPHYPACKET_TYPE_PING 0x00000000
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#define EXTPHYPACKET_TYPE_REMOTEACCESS_BASE 0x00040000
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#define EXTPHYPACKET_TYPE_REMOTEACCESS_PAGED 0x00140000
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#define EXTPHYPACKET_TYPE_REMOTEREPLY_BASE 0x000C0000
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#define EXTPHYPACKET_TYPE_REMOTEREPLY_PAGED 0x001C0000
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#define EXTPHYPACKET_TYPE_REMOTECOMMAND 0x00200000
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#define EXTPHYPACKET_TYPE_REMOTECONFIRMATION 0x00280000
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#define EXTPHYPACKET_TYPE_RESUME 0x003C0000
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#define EXTPHYPACKET_TYPEMASK 0xC0FC0000
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#define PHYPACKET_PORT_SHIFT 24
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#define PHYPACKET_GAPCOUNT_SHIFT 16
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/* 1394a PHY register map bitmasks */
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#define PHY_00_PHYSICAL_ID 0xFC
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#define PHY_00_R 0x02 /* Root */
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#define PHY_00_PS 0x01 /* Power Status*/
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#define PHY_01_RHB 0x80 /* Root Hold-Off */
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#define PHY_01_IBR 0x80 /* Initiate Bus Reset */
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#define PHY_01_GAP_COUNT 0x3F
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#define PHY_02_EXTENDED 0xE0 /* 0x7 for 1394a-compliant PHY */
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#define PHY_02_TOTAL_PORTS 0x1F
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#define PHY_03_MAX_SPEED 0xE0
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#define PHY_03_DELAY 0x0F
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#define PHY_04_LCTRL 0x80 /* Link Active Report Control */
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#define PHY_04_CONTENDER 0x40
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#define PHY_04_JITTER 0x38
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#define PHY_04_PWR_CLASS 0x07 /* Power Class */
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#define PHY_05_WATCHDOG 0x80
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#define PHY_05_ISBR 0x40 /* Initiate Short Bus Reset */
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#define PHY_05_LOOP 0x20 /* Loop Detect */
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#define PHY_05_PWR_FAIL 0x10 /* Cable Power Failure Detect */
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#define PHY_05_TIMEOUT 0x08 /* Arbitration State Machine Timeout */
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#define PHY_05_PORT_EVENT 0x04 /* Port Event Detect */
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#define PHY_05_ENAB_ACCEL 0x02 /* Enable Arbitration Acceleration */
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#define PHY_05_ENAB_MULTI 0x01 /* Ena. Multispeed Packet Concatenation */
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#include <asm/byteorder.h>
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#ifdef __BIG_ENDIAN_BITFIELD
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struct selfid {
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u32 packet_identifier:2; /* always binary 10 */
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u32 phy_id:6;
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/* byte */
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u32 extended:1; /* if true is struct ext_selfid */
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u32 link_active:1;
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u32 gap_count:6;
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/* byte */
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u32 speed:2;
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u32 phy_delay:2;
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u32 contender:1;
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u32 power_class:3;
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/* byte */
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u32 port0:2;
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u32 port1:2;
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u32 port2:2;
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u32 initiated_reset:1;
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u32 more_packets:1;
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} __attribute__((packed));
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struct ext_selfid {
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u32 packet_identifier:2; /* always binary 10 */
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u32 phy_id:6;
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/* byte */
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u32 extended:1; /* if false is struct selfid */
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u32 seq_nr:3;
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u32 reserved:2;
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u32 porta:2;
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/* byte */
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u32 portb:2;
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u32 portc:2;
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u32 portd:2;
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u32 porte:2;
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/* byte */
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u32 portf:2;
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u32 portg:2;
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u32 porth:2;
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u32 reserved2:1;
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u32 more_packets:1;
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} __attribute__((packed));
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#elif defined __LITTLE_ENDIAN_BITFIELD /* __BIG_ENDIAN_BITFIELD */
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/*
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* Note: these mean to be bit fields of a big endian SelfID as seen on a little
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* endian machine. Without swapping.
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*/
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struct selfid {
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u32 phy_id:6;
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u32 packet_identifier:2; /* always binary 10 */
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/* byte */
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u32 gap_count:6;
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u32 link_active:1;
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u32 extended:1; /* if true is struct ext_selfid */
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/* byte */
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u32 power_class:3;
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u32 contender:1;
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u32 phy_delay:2;
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u32 speed:2;
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/* byte */
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u32 more_packets:1;
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u32 initiated_reset:1;
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u32 port2:2;
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u32 port1:2;
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u32 port0:2;
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} __attribute__((packed));
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struct ext_selfid {
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u32 phy_id:6;
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u32 packet_identifier:2; /* always binary 10 */
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/* byte */
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u32 porta:2;
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u32 reserved:2;
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u32 seq_nr:3;
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u32 extended:1; /* if false is struct selfid */
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/* byte */
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u32 porte:2;
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u32 portd:2;
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u32 portc:2;
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u32 portb:2;
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/* byte */
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u32 more_packets:1;
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u32 reserved2:1;
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u32 porth:2;
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u32 portg:2;
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u32 portf:2;
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} __attribute__((packed));
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#else
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#error What? PDP endian?
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#endif /* __BIG_ENDIAN_BITFIELD */
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#endif /* _IEEE1394_IEEE1394_H */
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