624 lines
15 KiB
C
624 lines
15 KiB
C
/*
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* Copyright 2009 Jerome Glisse.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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* Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
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* Dave Airlie
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*/
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#include <linux/list.h>
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#include <linux/slab.h>
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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#include "radeon_trace.h"
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int radeon_ttm_init(struct radeon_device *rdev);
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void radeon_ttm_fini(struct radeon_device *rdev);
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static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
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/*
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* To exclude mutual BO access we rely on bo_reserve exclusion, as all
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* function are calling it.
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*/
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void radeon_bo_clear_va(struct radeon_bo *bo)
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{
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struct radeon_bo_va *bo_va, *tmp;
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list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
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/* remove from all vm address space */
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radeon_vm_bo_rmv(bo->rdev, bo_va);
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}
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}
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static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
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{
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struct radeon_bo *bo;
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bo = container_of(tbo, struct radeon_bo, tbo);
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mutex_lock(&bo->rdev->gem.mutex);
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list_del_init(&bo->list);
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mutex_unlock(&bo->rdev->gem.mutex);
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radeon_bo_clear_surface_reg(bo);
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radeon_bo_clear_va(bo);
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drm_gem_object_release(&bo->gem_base);
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kfree(bo);
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}
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bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
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{
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if (bo->destroy == &radeon_ttm_bo_destroy)
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return true;
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return false;
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}
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void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
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{
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u32 c = 0;
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rbo->placement.fpfn = 0;
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rbo->placement.lpfn = 0;
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rbo->placement.placement = rbo->placements;
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rbo->placement.busy_placement = rbo->placements;
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if (domain & RADEON_GEM_DOMAIN_VRAM)
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rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
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TTM_PL_FLAG_VRAM;
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if (domain & RADEON_GEM_DOMAIN_GTT) {
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if (rbo->rdev->flags & RADEON_IS_AGP) {
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rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT;
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} else {
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rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT;
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}
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}
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if (domain & RADEON_GEM_DOMAIN_CPU) {
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if (rbo->rdev->flags & RADEON_IS_AGP) {
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rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM;
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} else {
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rbo->placements[c++] = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM;
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}
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}
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if (!c)
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rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
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rbo->placement.num_placement = c;
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rbo->placement.num_busy_placement = c;
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}
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int radeon_bo_create(struct radeon_device *rdev,
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unsigned long size, int byte_align, bool kernel, u32 domain,
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struct sg_table *sg, struct radeon_bo **bo_ptr)
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{
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struct radeon_bo *bo;
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enum ttm_bo_type type;
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unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
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size_t acc_size;
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int r;
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size = ALIGN(size, PAGE_SIZE);
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rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
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if (kernel) {
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type = ttm_bo_type_kernel;
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} else if (sg) {
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type = ttm_bo_type_sg;
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} else {
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type = ttm_bo_type_device;
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}
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*bo_ptr = NULL;
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acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
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sizeof(struct radeon_bo));
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bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
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if (bo == NULL)
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return -ENOMEM;
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r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
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if (unlikely(r)) {
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kfree(bo);
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return r;
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}
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bo->rdev = rdev;
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bo->surface_reg = -1;
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INIT_LIST_HEAD(&bo->list);
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INIT_LIST_HEAD(&bo->va);
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radeon_ttm_placement_from_domain(bo, domain);
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/* Kernel allocation are uninterruptible */
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down_read(&rdev->pm.mclk_lock);
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r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
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&bo->placement, page_align, !kernel, NULL,
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acc_size, sg, &radeon_ttm_bo_destroy);
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up_read(&rdev->pm.mclk_lock);
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if (unlikely(r != 0)) {
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return r;
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}
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*bo_ptr = bo;
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trace_radeon_bo_create(bo);
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return 0;
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}
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int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
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{
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bool is_iomem;
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int r;
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if (bo->kptr) {
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if (ptr) {
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*ptr = bo->kptr;
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}
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return 0;
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}
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r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
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if (r) {
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return r;
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}
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bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
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if (ptr) {
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*ptr = bo->kptr;
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}
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radeon_bo_check_tiling(bo, 0, 0);
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return 0;
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}
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void radeon_bo_kunmap(struct radeon_bo *bo)
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{
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if (bo->kptr == NULL)
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return;
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bo->kptr = NULL;
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radeon_bo_check_tiling(bo, 0, 0);
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ttm_bo_kunmap(&bo->kmap);
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}
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void radeon_bo_unref(struct radeon_bo **bo)
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{
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struct ttm_buffer_object *tbo;
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struct radeon_device *rdev;
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if ((*bo) == NULL)
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return;
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rdev = (*bo)->rdev;
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tbo = &((*bo)->tbo);
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down_read(&rdev->pm.mclk_lock);
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ttm_bo_unref(&tbo);
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up_read(&rdev->pm.mclk_lock);
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if (tbo == NULL)
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*bo = NULL;
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}
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int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
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u64 *gpu_addr)
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{
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int r, i;
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if (bo->pin_count) {
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bo->pin_count++;
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if (gpu_addr)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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if (max_offset != 0) {
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u64 domain_start;
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if (domain == RADEON_GEM_DOMAIN_VRAM)
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domain_start = bo->rdev->mc.vram_start;
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else
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domain_start = bo->rdev->mc.gtt_start;
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WARN_ON_ONCE(max_offset <
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(radeon_bo_gpu_offset(bo) - domain_start));
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}
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return 0;
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}
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radeon_ttm_placement_from_domain(bo, domain);
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if (domain == RADEON_GEM_DOMAIN_VRAM) {
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/* force to pin into visible video ram */
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bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
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}
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if (max_offset) {
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u64 lpfn = max_offset >> PAGE_SHIFT;
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if (!bo->placement.lpfn)
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bo->placement.lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT;
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if (lpfn < bo->placement.lpfn)
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bo->placement.lpfn = lpfn;
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}
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for (i = 0; i < bo->placement.num_placement; i++)
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bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (likely(r == 0)) {
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bo->pin_count = 1;
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if (gpu_addr != NULL)
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*gpu_addr = radeon_bo_gpu_offset(bo);
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}
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if (unlikely(r != 0))
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dev_err(bo->rdev->dev, "%p pin failed\n", bo);
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return r;
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}
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int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
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{
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return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
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}
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int radeon_bo_unpin(struct radeon_bo *bo)
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{
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int r, i;
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if (!bo->pin_count) {
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dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
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return 0;
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}
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bo->pin_count--;
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if (bo->pin_count)
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return 0;
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for (i = 0; i < bo->placement.num_placement; i++)
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bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
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r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
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if (unlikely(r != 0))
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dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
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return r;
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}
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int radeon_bo_evict_vram(struct radeon_device *rdev)
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{
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/* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
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if (0 && (rdev->flags & RADEON_IS_IGP)) {
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if (rdev->mc.igp_sideport_enabled == false)
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/* Useless to evict on IGP chips */
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return 0;
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}
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return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
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}
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void radeon_bo_force_delete(struct radeon_device *rdev)
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{
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struct radeon_bo *bo, *n;
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if (list_empty(&rdev->gem.objects)) {
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return;
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}
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dev_err(rdev->dev, "Userspace still has active objects !\n");
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list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
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mutex_lock(&rdev->ddev->struct_mutex);
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dev_err(rdev->dev, "%p %p %lu %lu force free\n",
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&bo->gem_base, bo, (unsigned long)bo->gem_base.size,
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*((unsigned long *)&bo->gem_base.refcount));
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mutex_lock(&bo->rdev->gem.mutex);
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list_del_init(&bo->list);
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mutex_unlock(&bo->rdev->gem.mutex);
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/* this should unref the ttm bo */
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drm_gem_object_unreference(&bo->gem_base);
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mutex_unlock(&rdev->ddev->struct_mutex);
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}
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}
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int radeon_bo_init(struct radeon_device *rdev)
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{
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/* Add an MTRR for the VRAM */
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if (!rdev->fastfb_working) {
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rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
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rdev->mc.aper_size);
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}
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DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
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rdev->mc.mc_vram_size >> 20,
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(unsigned long long)rdev->mc.aper_size >> 20);
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DRM_INFO("RAM width %dbits %cDR\n",
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rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
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return radeon_ttm_init(rdev);
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}
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void radeon_bo_fini(struct radeon_device *rdev)
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{
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radeon_ttm_fini(rdev);
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arch_phys_wc_del(rdev->mc.vram_mtrr);
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}
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void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
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struct list_head *head)
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{
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if (lobj->written) {
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list_add(&lobj->tv.head, head);
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} else {
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list_add_tail(&lobj->tv.head, head);
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}
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}
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int radeon_bo_list_validate(struct ww_acquire_ctx *ticket,
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struct list_head *head, int ring)
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{
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struct radeon_bo_list *lobj;
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struct radeon_bo *bo;
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u32 domain;
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int r;
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r = ttm_eu_reserve_buffers(ticket, head);
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if (unlikely(r != 0)) {
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return r;
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}
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list_for_each_entry(lobj, head, tv.head) {
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bo = lobj->bo;
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if (!bo->pin_count) {
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domain = lobj->domain;
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retry:
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radeon_ttm_placement_from_domain(bo, domain);
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if (ring == R600_RING_TYPE_UVD_INDEX)
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radeon_uvd_force_into_uvd_segment(bo);
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r = ttm_bo_validate(&bo->tbo, &bo->placement,
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true, false);
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if (unlikely(r)) {
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if (r != -ERESTARTSYS && domain != lobj->alt_domain) {
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domain = lobj->alt_domain;
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goto retry;
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}
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ttm_eu_backoff_reservation(ticket, head);
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return r;
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}
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}
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lobj->gpu_offset = radeon_bo_gpu_offset(bo);
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lobj->tiling_flags = bo->tiling_flags;
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}
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return 0;
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}
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int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
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struct vm_area_struct *vma)
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{
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return ttm_fbdev_mmap(vma, &bo->tbo);
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}
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int radeon_bo_get_surface_reg(struct radeon_bo *bo)
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{
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struct radeon_device *rdev = bo->rdev;
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struct radeon_surface_reg *reg;
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struct radeon_bo *old_object;
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int steal;
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int i;
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lockdep_assert_held(&bo->tbo.resv->lock.base);
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if (!bo->tiling_flags)
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return 0;
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if (bo->surface_reg >= 0) {
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reg = &rdev->surface_regs[bo->surface_reg];
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i = bo->surface_reg;
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goto out;
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}
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steal = -1;
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for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
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reg = &rdev->surface_regs[i];
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if (!reg->bo)
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break;
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old_object = reg->bo;
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if (old_object->pin_count == 0)
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steal = i;
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}
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/* if we are all out */
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if (i == RADEON_GEM_MAX_SURFACES) {
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if (steal == -1)
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return -ENOMEM;
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/* find someone with a surface reg and nuke their BO */
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reg = &rdev->surface_regs[steal];
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old_object = reg->bo;
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/* blow away the mapping */
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DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
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ttm_bo_unmap_virtual(&old_object->tbo);
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old_object->surface_reg = -1;
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i = steal;
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}
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bo->surface_reg = i;
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reg->bo = bo;
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out:
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radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
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bo->tbo.mem.start << PAGE_SHIFT,
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bo->tbo.num_pages << PAGE_SHIFT);
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return 0;
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}
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static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
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{
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struct radeon_device *rdev = bo->rdev;
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struct radeon_surface_reg *reg;
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if (bo->surface_reg == -1)
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return;
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reg = &rdev->surface_regs[bo->surface_reg];
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radeon_clear_surface_reg(rdev, bo->surface_reg);
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reg->bo = NULL;
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bo->surface_reg = -1;
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}
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int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
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uint32_t tiling_flags, uint32_t pitch)
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{
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struct radeon_device *rdev = bo->rdev;
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int r;
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if (rdev->family >= CHIP_CEDAR) {
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unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
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bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
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bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
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mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
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tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
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stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
|
|
switch (bankw) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
switch (bankh) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
switch (mtaspect) {
|
|
case 0:
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
if (tilesplit > 6) {
|
|
return -EINVAL;
|
|
}
|
|
if (stilesplit > 6) {
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
r = radeon_bo_reserve(bo, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
bo->tiling_flags = tiling_flags;
|
|
bo->pitch = pitch;
|
|
radeon_bo_unreserve(bo);
|
|
return 0;
|
|
}
|
|
|
|
void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
|
|
uint32_t *tiling_flags,
|
|
uint32_t *pitch)
|
|
{
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
if (tiling_flags)
|
|
*tiling_flags = bo->tiling_flags;
|
|
if (pitch)
|
|
*pitch = bo->pitch;
|
|
}
|
|
|
|
int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
|
|
bool force_drop)
|
|
{
|
|
if (!force_drop)
|
|
lockdep_assert_held(&bo->tbo.resv->lock.base);
|
|
|
|
if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
|
|
return 0;
|
|
|
|
if (force_drop) {
|
|
radeon_bo_clear_surface_reg(bo);
|
|
return 0;
|
|
}
|
|
|
|
if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
|
|
if (!has_moved)
|
|
return 0;
|
|
|
|
if (bo->surface_reg >= 0)
|
|
radeon_bo_clear_surface_reg(bo);
|
|
return 0;
|
|
}
|
|
|
|
if ((bo->surface_reg >= 0) && !has_moved)
|
|
return 0;
|
|
|
|
return radeon_bo_get_surface_reg(bo);
|
|
}
|
|
|
|
void radeon_bo_move_notify(struct ttm_buffer_object *bo,
|
|
struct ttm_mem_reg *mem)
|
|
{
|
|
struct radeon_bo *rbo;
|
|
if (!radeon_ttm_bo_is_radeon_bo(bo))
|
|
return;
|
|
rbo = container_of(bo, struct radeon_bo, tbo);
|
|
radeon_bo_check_tiling(rbo, 0, 1);
|
|
radeon_vm_bo_invalidate(rbo->rdev, rbo);
|
|
}
|
|
|
|
int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
|
|
{
|
|
struct radeon_device *rdev;
|
|
struct radeon_bo *rbo;
|
|
unsigned long offset, size;
|
|
int r;
|
|
|
|
if (!radeon_ttm_bo_is_radeon_bo(bo))
|
|
return 0;
|
|
rbo = container_of(bo, struct radeon_bo, tbo);
|
|
radeon_bo_check_tiling(rbo, 0, 0);
|
|
rdev = rbo->rdev;
|
|
if (bo->mem.mem_type == TTM_PL_VRAM) {
|
|
size = bo->mem.num_pages << PAGE_SHIFT;
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
if ((offset + size) > rdev->mc.visible_vram_size) {
|
|
/* hurrah the memory is not visible ! */
|
|
radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
|
|
rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
|
|
r = ttm_bo_validate(bo, &rbo->placement, false, false);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
offset = bo->mem.start << PAGE_SHIFT;
|
|
/* this should not happen */
|
|
if ((offset + size) > rdev->mc.visible_vram_size)
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
|
|
{
|
|
int r;
|
|
|
|
r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
|
|
if (unlikely(r != 0))
|
|
return r;
|
|
spin_lock(&bo->tbo.bdev->fence_lock);
|
|
if (mem_type)
|
|
*mem_type = bo->tbo.mem.mem_type;
|
|
if (bo->tbo.sync_obj)
|
|
r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
|
|
spin_unlock(&bo->tbo.bdev->fence_lock);
|
|
ttm_bo_unreserve(&bo->tbo);
|
|
return r;
|
|
}
|