75 lines
3.0 KiB
C
75 lines
3.0 KiB
C
/*
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* File: arch/blackfin/mach-bf537/ints-priority.c
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* Based on: arch/blackfin/mach-bf533/ints-priority.c
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* Author: Michael Hennerich
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*
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* Created:
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* Description: Set up the interrupt priorities
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*
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* Modified:
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* Copyright 2004-2006 Analog Devices Inc.
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*
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see the file COPYING, or write
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* to the Free Software Foundation, Inc.,
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* 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/module.h>
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#include <linux/irq.h>
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#include <asm/blackfin.h>
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void __init program_IAR(void)
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{
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/* Program the IAR0 Register with the configured priority */
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bfin_write_SIC_IAR0(((CONFIG_IRQ_PLL_WAKEUP - 7) << IRQ_PLL_WAKEUP_POS) |
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((CONFIG_IRQ_DMA_ERROR - 7) << IRQ_DMA_ERROR_POS) |
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((CONFIG_IRQ_ERROR - 7) << IRQ_ERROR_POS) |
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((CONFIG_IRQ_RTC - 7) << IRQ_RTC_POS) |
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((CONFIG_IRQ_PPI - 7) << IRQ_PPI_POS) |
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((CONFIG_IRQ_SPORT0_RX - 7) << IRQ_SPORT0_RX_POS) |
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((CONFIG_IRQ_SPORT0_TX - 7) << IRQ_SPORT0_TX_POS) |
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((CONFIG_IRQ_SPORT1_RX - 7) << IRQ_SPORT1_RX_POS));
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bfin_write_SIC_IAR1(((CONFIG_IRQ_SPORT1_TX - 7) << IRQ_SPORT1_TX_POS) |
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((CONFIG_IRQ_TWI - 7) << IRQ_TWI_POS) |
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((CONFIG_IRQ_SPI - 7) << IRQ_SPI_POS) |
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((CONFIG_IRQ_UART0_RX - 7) << IRQ_UART0_RX_POS) |
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((CONFIG_IRQ_UART0_TX - 7) << IRQ_UART0_TX_POS) |
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((CONFIG_IRQ_UART1_RX - 7) << IRQ_UART1_RX_POS) |
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((CONFIG_IRQ_UART1_TX - 7) << IRQ_UART1_TX_POS) |
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((CONFIG_IRQ_CAN_RX - 7) << IRQ_CAN_RX_POS));
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bfin_write_SIC_IAR2(((CONFIG_IRQ_CAN_TX - 7) << IRQ_CAN_TX_POS) |
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((CONFIG_IRQ_MAC_RX - 7) << IRQ_MAC_RX_POS) |
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((CONFIG_IRQ_MAC_TX - 7) << IRQ_MAC_TX_POS) |
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((CONFIG_IRQ_TMR0 - 7) << IRQ_TMR0_POS) |
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((CONFIG_IRQ_TMR1 - 7) << IRQ_TMR1_POS) |
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((CONFIG_IRQ_TMR2 - 7) << IRQ_TMR2_POS) |
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((CONFIG_IRQ_TMR3 - 7) << IRQ_TMR3_POS) |
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((CONFIG_IRQ_TMR4 - 7) << IRQ_TMR4_POS));
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bfin_write_SIC_IAR3(((CONFIG_IRQ_TMR5 - 7) << IRQ_TMR5_POS) |
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((CONFIG_IRQ_TMR6 - 7) << IRQ_TMR6_POS) |
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((CONFIG_IRQ_TMR7 - 7) << IRQ_TMR7_POS) |
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((CONFIG_IRQ_PROG_INTA - 7) << IRQ_PROG_INTA_POS) |
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((CONFIG_IRQ_PORTG_INTB - 7) << IRQ_PORTG_INTB_POS) |
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((CONFIG_IRQ_MEM_DMA0 - 7) << IRQ_MEM_DMA0_POS) |
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((CONFIG_IRQ_MEM_DMA1 - 7) << IRQ_MEM_DMA1_POS) |
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((CONFIG_IRQ_WATCH - 7) << IRQ_WATCH_POS));
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SSYNC();
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}
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