237 lines
6.3 KiB
C
237 lines
6.3 KiB
C
/*
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*
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* Alchemy Au1x00 ethernet driver include file
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*
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* Author: Pete Popov <ppopov@mvista.com>
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*
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* Copyright 2001 MontaVista Software Inc.
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*
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* ########################################################################
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License (Version 2) as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* ########################################################################
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*
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*
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*/
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#define MAC_IOSIZE 0x10000
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#define NUM_RX_DMA 4 /* Au1x00 has 4 rx hardware descriptors */
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#define NUM_TX_DMA 4 /* Au1x00 has 4 tx hardware descriptors */
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#define NUM_RX_BUFFS 4
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#define NUM_TX_BUFFS 4
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#define MAX_BUF_SIZE 2048
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#define ETH_TX_TIMEOUT HZ/4
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#define MAC_MIN_PKT_SIZE 64
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#define MULTICAST_FILTER_LIMIT 64
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/* FIXME
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* The PHY defines should be in a separate file.
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*/
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/* MII register offsets */
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#define MII_CONTROL 0x0000
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#define MII_STATUS 0x0001
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#define MII_PHY_ID0 0x0002
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#define MII_PHY_ID1 0x0003
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#define MII_ANADV 0x0004
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#define MII_ANLPAR 0x0005
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#define MII_AEXP 0x0006
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#define MII_ANEXT 0x0007
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#define MII_LSI_PHY_CONFIG 0x0011
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/* Status register */
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#define MII_LSI_PHY_STAT 0x0012
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#define MII_AMD_PHY_STAT MII_LSI_PHY_STAT
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#define MII_INTEL_PHY_STAT 0x0011
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#define MII_AUX_CNTRL 0x0018
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/* mii registers specific to AMD 79C901 */
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#define MII_STATUS_SUMMARY = 0x0018
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/* MII Control register bit definitions. */
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#define MII_CNTL_FDX 0x0100
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#define MII_CNTL_RST_AUTO 0x0200
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#define MII_CNTL_ISOLATE 0x0400
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#define MII_CNTL_PWRDWN 0x0800
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#define MII_CNTL_AUTO 0x1000
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#define MII_CNTL_F100 0x2000
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#define MII_CNTL_LPBK 0x4000
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#define MII_CNTL_RESET 0x8000
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/* MII Status register bit */
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#define MII_STAT_EXT 0x0001
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#define MII_STAT_JAB 0x0002
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#define MII_STAT_LINK 0x0004
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#define MII_STAT_CAN_AUTO 0x0008
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#define MII_STAT_FAULT 0x0010
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#define MII_STAT_AUTO_DONE 0x0020
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#define MII_STAT_CAN_T 0x0800
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#define MII_STAT_CAN_T_FDX 0x1000
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#define MII_STAT_CAN_TX 0x2000
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#define MII_STAT_CAN_TX_FDX 0x4000
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#define MII_STAT_CAN_T4 0x8000
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#define MII_ID1_OUI_LO 0xFC00 /* low bits of OUI mask */
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#define MII_ID1_MODEL 0x03F0 /* model number */
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#define MII_ID1_REV 0x000F /* model number */
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/* MII NWAY Register Bits ...
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valid for the ANAR (Auto-Negotiation Advertisement) and
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ANLPAR (Auto-Negotiation Link Partner) registers */
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#define MII_NWAY_NODE_SEL 0x001f
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#define MII_NWAY_CSMA_CD 0x0001
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#define MII_NWAY_T 0x0020
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#define MII_NWAY_T_FDX 0x0040
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#define MII_NWAY_TX 0x0080
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#define MII_NWAY_TX_FDX 0x0100
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#define MII_NWAY_T4 0x0200
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#define MII_NWAY_PAUSE 0x0400
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#define MII_NWAY_RF 0x2000 /* Remote Fault */
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#define MII_NWAY_ACK 0x4000 /* Remote Acknowledge */
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#define MII_NWAY_NP 0x8000 /* Next Page (Enable) */
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/* mii stsout register bits */
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#define MII_STSOUT_LINK_FAIL 0x4000
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#define MII_STSOUT_SPD 0x0080
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#define MII_STSOUT_DPLX 0x0040
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/* mii stsics register bits */
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#define MII_STSICS_SPD 0x8000
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#define MII_STSICS_DPLX 0x4000
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#define MII_STSICS_LINKSTS 0x0001
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/* mii stssum register bits */
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#define MII_STSSUM_LINK 0x0008
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#define MII_STSSUM_DPLX 0x0004
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#define MII_STSSUM_AUTO 0x0002
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#define MII_STSSUM_SPD 0x0001
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/* lsi phy status register */
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#define MII_LSI_PHY_STAT_FDX 0x0040
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#define MII_LSI_PHY_STAT_SPD 0x0080
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/* amd phy status register */
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#define MII_AMD_PHY_STAT_FDX 0x0800
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#define MII_AMD_PHY_STAT_SPD 0x0400
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/* intel phy status register */
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#define MII_INTEL_PHY_STAT_FDX 0x0200
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#define MII_INTEL_PHY_STAT_SPD 0x4000
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/* Auxilliary Control/Status Register */
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#define MII_AUX_FDX 0x0001
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#define MII_AUX_100 0x0002
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#define MII_AUX_F100 0x0004
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#define MII_AUX_ANEG 0x0008
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typedef struct mii_phy {
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struct mii_phy * next;
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struct mii_chip_info * chip_info;
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u16 status;
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u32 *mii_control_reg;
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u32 *mii_data_reg;
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} mii_phy_t;
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struct phy_ops {
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int (*phy_init) (struct net_device *, int);
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int (*phy_reset) (struct net_device *, int);
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int (*phy_status) (struct net_device *, int, u16 *, u16 *);
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};
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/*
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* Data Buffer Descriptor. Data buffers must be aligned on 32 byte
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* boundary for both, receive and transmit.
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*/
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typedef struct db_dest {
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struct db_dest *pnext;
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volatile u32 *vaddr;
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dma_addr_t dma_addr;
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} db_dest_t;
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/*
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* The transmit and receive descriptors are memory
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* mapped registers.
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*/
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typedef struct tx_dma {
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u32 status;
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u32 buff_stat;
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u32 len;
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u32 pad;
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} tx_dma_t;
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typedef struct rx_dma {
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u32 status;
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u32 buff_stat;
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u32 pad[2];
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} rx_dma_t;
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/*
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* MAC control registers, memory mapped.
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*/
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typedef struct mac_reg {
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u32 control;
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u32 mac_addr_high;
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u32 mac_addr_low;
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u32 multi_hash_high;
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u32 multi_hash_low;
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u32 mii_control;
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u32 mii_data;
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u32 flow_control;
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u32 vlan1_tag;
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u32 vlan2_tag;
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} mac_reg_t;
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struct au1000_private {
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db_dest_t *pDBfree;
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db_dest_t db[NUM_RX_BUFFS+NUM_TX_BUFFS];
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volatile rx_dma_t *rx_dma_ring[NUM_RX_DMA];
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volatile tx_dma_t *tx_dma_ring[NUM_TX_DMA];
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db_dest_t *rx_db_inuse[NUM_RX_DMA];
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db_dest_t *tx_db_inuse[NUM_TX_DMA];
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u32 rx_head;
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u32 tx_head;
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u32 tx_tail;
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u32 tx_full;
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int mac_id;
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mii_phy_t *mii;
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struct phy_ops *phy_ops;
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/* These variables are just for quick access to certain regs addresses. */
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volatile mac_reg_t *mac; /* mac registers */
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volatile u32 *enable; /* address of MAC Enable Register */
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u32 vaddr; /* virtual address of rx/tx buffers */
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dma_addr_t dma_addr; /* dma address of rx/tx buffers */
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u8 *hash_table;
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u32 hash_mode;
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u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */
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int phy_addr; /* phy address */
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u32 options; /* User-settable misc. driver options. */
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u32 drv_flags;
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int want_autoneg;
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struct net_device_stats stats;
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struct timer_list timer;
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spinlock_t lock; /* Serialise access to device */
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};
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